DS33Z41 Quad IMUX Ethernet Mapper

5 MAJOR OPERATING MODES

Operation of the DS33Z41 operation requires a host microprocessor for initialization and maintenance of the link aggregation functions. Microprocessor control is possible through the 8-bit parallel control port. More information on microprocessor control is available in Section 8.1.

6 BLOCK DIAGRAMS

Figure 6-1. Detailed Block Diagram

 

 

 

 

 

50 or 25

Mhz Oscillator

 

 

 

Microport

Buffer

REF_CLK

 

 

 

 

Div by 1,2,4,8,10

 

 

 

 

 

 

 

 

 

 

Output clocks:

 

 

 

 

 

 

50,25 Mhz,2.5 Mhz

 

 

TSER

 

 

 

 

 

 

TCLKI1

 

HDLC

 

 

TX_CLK1

 

 

 

 

 

 

 

+

 

 

RXD

 

 

 

 

MAC

 

 

Line 1

Serial

CIR

 

 

 

 

 

IMUX

Interface

RMII

RX_CLK1

 

RCLKI1

Arbiter

 

 

 

MII

 

 

 

 

 

TXD

 

RSER

 

X.86

 

 

 

 

 

 

 

 

 

 

 

 

 

MDC

 

 

 

JTAG

 

 

 

100 Mhz Oscillator

 

 

 

 

Buffer Dev

 

 

 

 

 

SDRAM

Div by 2,4,12

SYSCLKI

 

 

 

 

Output Clocks

 

 

 

 

 

Interface

25,50

 

 

 

 

 

 

Mhz

 

 

 

 

 

 

SDCLKO

 

 

 

 

 

 

REF_CLKO

 

 

 

 

 

 

50 or 25 Mhz

 

 

 

 

 

SDRAM

 

 

 

 

 

 

13 of 167

 

 

 

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Image 13
Maxim DS33Z41 specifications Major Operating Modes, Block Diagrams