DS33Z41 Quad IMUX Ethernet Mapper
Register Name: |
| LI.TPPSR |
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Register Description: |
| Transmit Packet Processor Status Register |
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Register Address: |
| 0C8h |
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Bit # | 7 | 6 | 5 | 4 | 3 |
| 2 | 1 | 0 | |
Name | — | — |
| — | — | — |
| — | — | TEPF |
Default | 0 | 0 |
| 0 | 0 | 0 |
| 0 | 0 | 0 |
Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated.
Register Name: |
| LI.TPPSRL |
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Register Description: |
| Transmit Packet Processor Status Register Latched |
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Register Address: |
| 0C9h |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 |
| 1 | 0 | |
Name | — | — |
| — | — | — | — |
| — | TEPFL |
Default | — | — |
| — | — | — | — |
| — | — |
Bit 0: Transmit Errored Packet Insertion Finished Latched (TEPFL). This bit is set when the TEPF bit in the TPPSR register transitions from zero to one.
Register Name: |
| LI.TPPSRIE |
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Register Description: |
| Transmit Packet Processor Status Register Interrupt Enable |
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Register Address: |
| 0CAh |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Name | — | — |
| — | — | — | — | — | TEPFIE |
Default | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 |
Bit 0: Transmit Errored Packet Insertion Finished Interrupt Enable (TEPFIE). This bit enables an interrupt if the TEPFL bit in the LI.TPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
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