DS33Z41 Quad IMUX Ethernet Mapper

Register Name:

 

LI.TPPSR

 

 

 

 

 

 

Register Description:

 

Transmit Packet Processor Status Register

 

 

 

Register Address:

 

0C8h

 

 

 

 

 

 

Bit #

7

6

5

4

3

 

2

1

0

Name

 

 

TEPF

Default

0

0

 

0

0

0

 

0

0

0

Bit 0: Transmit Errored Packet Insertion Finished (TEPF). This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted. This bit is cleared when errored packet insertion is disabled, or a new errored packet insertion process is initiated.

Register Name:

 

LI.TPPSRL

 

 

 

 

 

 

Register Description:

 

Transmit Packet Processor Status Register Latched

 

 

Register Address:

 

0C9h

 

 

 

 

 

 

Bit #

7

6

5

4

3

2

 

1

0

Name

 

 

TEPFL

Default

 

 

Bit 0: Transmit Errored Packet Insertion Finished Latched (TEPFL). This bit is set when the TEPF bit in the TPPSR register transitions from zero to one.

Register Name:

 

LI.TPPSRIE

 

 

 

 

 

Register Description:

 

Transmit Packet Processor Status Register Interrupt Enable

 

Register Address:

 

0CAh

 

 

 

 

 

Bit #

7

6

5

4

3

2

1

0

Name

 

TEPFIE

Default

0

0

 

0

0

0

0

0

0

Bit 0: Transmit Errored Packet Insertion Finished Interrupt Enable (TEPFIE). This bit enables an interrupt if the TEPFL bit in the LI.TPPSRL register is set.

0 = interrupt disabled

1 = interrupt enabled

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Maxim DS33Z41 specifications Li.Tppsrl, Li.Tppsrie