Maxim DS33Z41 specifications SU.RFSB3, 157h, Mcf

Models: DS33Z41

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DS33Z41 Quad IMUX Ethernet Mapper

Register Name:

 

SU.RFSB3

 

 

 

 

 

 

Register Description:

 

Receive Frame Status Byte 3

 

 

 

 

Register Address:

 

157h

 

 

 

 

 

 

Bit #

7

6

5

4

 

3

2

1

0

Name

MF

 

BF

 

MCF

UF

CF

LE

Default

0

0

 

0

0

 

0

0

0

0

Bit 7: Missed Frame (MF). This bit is set to 1 if the packet is not successfully received from the MAC by the packet Arbiter.

Bit 4: Broadcast Frame (BF). This bit is set to 1 if the current frame is a broadcast frame.

Bit 3: Multicast Frame (MCF). This bit is set to 1 if the current frame is a multicast frame.

Bit 2: Unsupported Control Frame (UF). This bit is set to 1 if the frame received is a control frame with an opcode that is not supported. If the Control Frame bit is set, and the Unsupported Control Frame bit is clear, then a pause frame has been received and the transmitter is paused.

Bit 1: Control Frame (CF). This bit is set to 1 when the current frame is a control frame. This bit is only valid in full-duplex mode.

Bit 0: Length Error (LE). This bit is set to 1 when the frames length field and the actual byte count are unequal. This bit is only valid for 802.3 frames.

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Page 120
Image 120
Maxim DS33Z41 specifications SU.RFSB3, 157h, Mcf