Maxim DS33Z41 9.5.3 Transmit HDLC Processor Registers

DS33Z41 Quad IMUX Ethernet Mapper

90 of 167

9.5.3 Transmit HDLC Processor Registers

Register Name: LI.TPPCL

Register Description: Transmit Packet Processor Control Low Register

Register Address: 0C4h

Bit # 7 6 5 4 3 2 1 0

Name — — TFAD TF16 TIFV TSD TBRE TIAEI

Default 0 0 0 0 0 0 0 0

Note: The user should take care not to modify this register value during packet error insertion.

Bit 5: Transmit FCS Append Disable (TFAD). This bit controls whether or not an FCS is appended to the end of

each packet. When equal to 0, the calculated FCS bytes are appended to packets. When set to 1, packets are

transmitted without FCS. In X.86 Mode, FCS is always 32 bits and is always appended to the packet.

Bit 4: Transmit FCS-16 Enable (TF16). When 0, the FCS processing uses a 32-bit FCS. When 1, the FCS

processing uses a 16-bit FCS. In X.86 Mode, 32-bit FCS processing is enabled.

Bit 3: Transmit Bit Synchronous Inter-Frame Fill Value (TIFV). When 0, inter-frame fill is done with the flag

sequence (7Eh). When 1, inter-frame fill is done with all ones. This bit is ignored in byte synchronous mode. In

X.86 mode the interframe flag is always 7E.

Bit 2: Transmit Scrambling Disable (TSD). When equal to 0, X43+1 scrambling is performed. When set to 1,

scrambling is disabled. Note that in hardware mode, transmit scrambling is controlled by the SCD hardware pin.

Bit 1: Transmit Bit Reordering Enable (TBRE). When equal to 0, bit reordering is disabled (The first bit

transmitted is from the MSB of the transmit FIFO byte TFD [7]). When set to 1, bit reordering is enabled (The first

bit transmitted is from the LSB of the transmit FIFO byte TFD [0]). Note that this function can be controlled in

Hardware mode with the BREO hardware pin.

Bit 0: Transmit Initiate Automatic Error Insertion (TIAEI). This write-only bit initiates error insertion. See the

LI.TEPHC register definition for details of usage.

Contents

Main GENERAL DESCRIPTION FUNCTIONAL DIAGRAM FEATURES DS33Z41 Quad IMUX Ethernet Mapper www.maxim-ic.com TABLE OF CONTENTS Page Page LIST OF FIGURES LIST OF TABLES 1 DESCRIPTION 2 FEATURE HIGHLIGHTS 2.1 General 2.2 Link Aggregation (Inverse Multiplexing) 2.3 HDLC 2.4 Committed Information Rate (CIR) Controller 2.6 SDRAM Interface 2.7 MAC Interface 2.8 Microprocessor Interface 2.9 Test and Diagnostics 2.10 Specifications compliance Table 2-1. T1 Related Telecommunications Specifications 3 APPLICATIONS Figure 3-1. Quad T1/E1 SCT to DS33Z41 4 ACRONYMS AND GLOSSARY TIME SLOT NUMBERING SCHEMES DS33Z41 Quad IMUX Ethernet Mapper 13 of 167 5 MAJOR OPERATING MODES 6 BLOCK DIAGRAMS Figure 6-1. Detailed Block Diagram SYSCLKI 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Table 7-1. Detailed Pin Descriptions Page Page Page Page Page Page Figure 7-1. DS33Z41 256-Ball CSBGA Pinout 8 FUNCTIONAL DESCRIPTION 8.1 Processor Interface 8.1.1 Read-Write/Data Strobe Modes 8.1.2 Clear on Read 8.1.3 Interrupt and Pin Modes 8.2 Clock Structure Table 8-1. Clock Selection for the Ethernet (LAN) Interface Figure 8-1. Clocking for the DS33Z41 SYSCLKI 8.2.1 Serial Interface Clock Modes 8.2.2 Ethernet Interface Clock Modes 8.3 Resets and Low-Power Modes Table 8-2. Reset Functions 8.4 Initialization and Configuration 8.5 Global Resources 8.6 Per-Port Resources 8.7 Device Interrupts DS33Z41 Quad IMUX Ethernet Mapper 30 of 167 Figure 8-2. Device Interrupt Information Flow Diagram GL.IMXOOFIE GL.IMXDFDELS GL.IMXSLS GL.IBIS 8.8 Serial Interface 8.9 Link Aggregation (IMUX) Figure 8-3. IMUX Interface to T1/E1 Transceivers Figure 8-4. Diagram of Data Transmission with IMUX Operation Sequence 01 Sequence 02 B 8.9.1 Microprocessor Requirements 8.9.2 IMUX Command Protocol Figure 8-5. Command Structure for IMUX Function Table 8-3. Commands Sent and Received on the IMUX Links Table 8-4. Command and Status for the IMUX for Processor Communication 8.9.3 Out of Frame (OOF) Monitoring 8.9.4 Data Transfer 8.10 Connections and Queues Table 8-5. Registers Related to Connections and Queues 8.11 Arbiter 8.12 Flow Control Table 8-6. Options for Flow Control 8.12.1 Full-Duplex Flow Control Figure 8-6. Flow Control Using Pause Control Frame 8.12.2 Half-Duplex Flow control 8.12.3 Host-Managed Flow control 8.13 Ethernet Interface Port Figure 8-7. IEEE 802.3 Ethernet Frame Table 8-7. Registers Related to the Ethernet Port 8.13.1 DTE and DCE Mode Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode Figure 8-9. DS33Z41 Configured as a DCE in MII Mode 8.14 Ethernet MAC Table 8-8. MAC Control Registers Table 8-9. MAC Status Registers 8.14.1 MII Mode 8.14.2 RMII Mode Figure 8-10. RMII Interface 8.14.3 PHY MII Management Block and MDI O Interface Figure 8-11. MII Management Frame 8.15 BERT 8.15.1 BERT Features 8.15.2 Receive Data Interface Figure 8-12. PRBS Synchronization State Diagram Sync LoadVerify 8.15.3 Repetitive Pattern Synchronization Figure 8-13. Repetitive Pattern Synchronization State Diagram Sync MatchVerify 8.15.4 Pattern Monitoring 8.15.5 Pattern Generation Page 8.16 Transmit Packet Processor 8.17 Receive Packet Processor Page 8.18 X.86 Encoding and Decoding Figure 8-14. LAPS Encoding of MAC Frames Concept Figure 8-15. X.86 Encapsulation of the MAC field Page 8.19 Committed Information Rate Controller Figure 8-16. CIR in the WAN Transmit Path 9 DEVICE REGISTERS Table 9-1. Register Address Map 9.1 Register Bit Maps 9.1.1 Global Register Bit Map Table 9-2. Global Register Bit Map 9.1.2 Arbiter Register Bit Map Table 9-3. Arbiter Register Bit Map 9.1.3 BERT Register Bit Map Table 9-4. BERT Register Bit Map 9.1.4 Serial Interface Register Bit Map Table 9-5. Serial Interface Register Bit Map Page 9.1.5 Ethernet Interface Register Bit Map Table 9-6. Ethernet Interface Register Bit Map 9.1.6 MAC Register Bit Map Table 9-7. MAC Indirect Register Bit Map Page 9.2 Global Register Definitions Page Page Page Page Page Page Page Page Page Page Page Page 9.3 Arbiter Registers 9.3.1 Arbiter Register Bit Descriptions 9.4 BERT Registers Page Page Page Page Page Page 9.5 Serial Interface Registers 9.5.1 Serial Interface Transmit and Common Registers 9.5.2 Serial Interface Transmit Register Bit Descriptions 9.5.3 Transmit HDLC Processor Registers Page Page Page Page Page Page 9.5.4 X.86 Registers Page 9.5.5 Receive Serial Interface Page Page Page Page Page Page Page Page Page Page Page Page 9.6 Ethernet Interface Registers 9.6.1 Ethernet Interface Register Bit Descriptions Page Page Page Page Page Page Page Page Page Page Page 9.6.2 MAC Registers Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 10 FUNCTIONAL TIMING 10.1 MII and RMII Interfaces Figure 10-1. MII Transmit Functional Timing Figure 10-2. MII Transmit Half Duplex with a Collision Functional Timing Figure 10-3. MII Receive Functional Timing Figure 10-4. RMII Transmit Interface Functional Timing Figure 10-5 RMII Receive Interface Functional Timing 11 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Table 11-1. Recommended DC Operating Conditions Table 11-2. DC Electrical Characteristics 11.1 Thermal Characteristics Table 11-3. Thermal Characteristics Table 11-4. Theta-JA vs. Airflow 11.2 MII Interface Table 11-5. Transmit MII Interface Figure 11-1. Transmit MII Interface Table 11-6. Receive MII Interface Figure 11-2. Receive MII Interface Timing 11.3 RMII Interface Table 11-7. Transmit RMII Interface Figure 11-3. Transmit RMII Interface Table 11-8. Receive RMII Interface Figure 11-4. Receive RMII Interface Timing 11.4 MDIO Interface Table 11-9. MDIO Interface Figure 11-5. MDIO Timing 11.5 Transmit WAN Interface Table 11-10. Transmit WAN Interface Figure 11-6. Transmit WAN Timing 11.6 Receive WAN Interface Table 11-11. Receive WAN Interface Figure 11-7. Receive WAN Timing 11.7 SDRAM Timing Table 11-12. SDRAM Interface Timing Figure 11-8. SDRAM Interface Timing Figure 11-9. Receive IBO Channel Interleave Mode Timing Figure 11-10. Transmit IBO Channel Interleave Mode Timing Page Figure 11-11. Intel Bus Read Timing (MODEC = 00) Figure 11-12. Intel Bus Write Timing (MODEC = 00) Figure 11-13. Motorola Bus Read Timing (MODEC = 01) Figure 11-14. Motorola Bus Write Timing (MODEC = 01) 11.9 JTAG Interface Timing Table 11-14. JTAG Interface Timing Figure 11-15. JTAG Interface Timing Diagram 12 JTAG INFORMATION Figure 12-1. JTAG Functional Block Diagram 12.1 JTAG TAP Controller State Machine Description Update-DR Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Figure 12-2. TAP Controller State Diagram 12.2 Instruction Register Table 12-1. Instruction Codes for IEEE 1149.1 Architecture 12.2.1 SAMPLE:PRELOAD 12.2.2 BYPASS 12.2.3 EXTEST 12.2.4 CLAMP 12.3 JTAG ID Codes Table 12-2. ID Code Structure 12.4 Test Registers 12.4.1 Boundary Scan Register 12.4.2 Bypass Register 12.4.3 Identification Register 12.5 JTAG Functional Timing Figure 12-3. JTAG Functional Timing Page 14 DOCUMENT REVISION HISTORY