Manuals / Maxim / Computer Equipment / Network Card

Maxim DS33Z41 specifications MAC Reserved Control Register, 010Ch indirect, 010Dh, 010Eh, 010Fh

Models: DS33Z41

1 167

Page 131

DS33Z41 Quad IMUX Ethernet Mapper

Register Name:		Reserved
Register Description:		MAC Reserved Control Register
Register Address:		010Ch (indirect)
010Ch:
Bit #	31	30	29	28	27	26	25	24
Name	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
Default	0	0	0	0	0	0	0	0
010Dh:
Bit #	23	22	21	20	19	18	17	16
Name	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
Default	0	0	0	0	0	0	0	0
010Eh:
Bit #	15	14	13	12	11	10	09	08
Name	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
Default	0	0	0	0	0	0	0	0
010Fh:
Bit #	07	06	05	04	03	02	01	00
Name	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
Default	0	0	0	0	0	0	0	0

Note: Addresses 10Ch through 10Fh must each be initialized with all ones (FFh) for proper software-mode operation.

131 of 167

Page 131

Image 131

Maxim DS33Z41 specifications MAC Reserved Control Register, 010Ch indirect, 010Dh, 010Eh, 010Fh

Contents

Applications Functional DiagramFeatures General DescriptionTable of Contents 140 166 List of Figures List of Tables Description Feature Highlights Microprocessor Interface Test and DiagnosticsSdram Interface MAC InterfaceT1 Related Telecommunications Specifications Specifications complianceQuad T1/E1 SCT to DS33Z41 Time Slot Acronyms and GlossaryMajor Operating Modes Block DiagramsMII/RMII Port Name PIN Type Function Serial Interface IO PinsPIN Descriptions Pin Functional Description Detailed Pin DescriptionsTransmit Data 0 through 1RMII. Two bits of data TXD Transmit Enable MIITransmit Enable Rmii Name PIN Type FunctionMicroprocessor Port ColdetMDC MdioMode Control Name PIN Type Function Sdram Controller Jtag Interface Queue StatusVSS Connect to the Common Supply Ground Name PIN Type Function Power SuppliesVDD3.3 Connect to 3.3V Power Supply VDD1.8 Connect to 1.8V Power SupplyC D E F G H J K L M N DS33Z41 256-Ball Csbga PinoutFunctional Description Interrupt and Pin Modes Processor InterfaceRead-Write/Data Strobe Modes Clear on ReadDTE Input Clock StructureClock Selection for the Ethernet LAN Interface Rmiimiis Speed DCE Refclko Rxclk Txclk MDC Output PINClocking for the DS33Z41 Ethernet Interface Clock Modes Serial Interface Clock ModesReset Function Location Comments Resets and Low-Power ModesReset Functions Example Device Initialization Sequence Initialization and ConfigurationGlobal Resources Per-Port ResourcesDevice Interrupts Interrupt Pin Drawing LegendLink Aggregation Imux Serial InterfaceSequence Imux Interface to T1/E1 TransceiversMicroprocessor Requirements OOF Commands Sent and Received on the Imux LinksImux Command Protocol Register Name Comments Command and Status for the Imux for Processor CommunicationData Transfer Out of Frame OOF MonitoringConnections and Queues Register Function Registers Related to Connections and QueuesArbiter Options for Flow Control Option ModeFlow Control Full-Duplex Flow Control Host-Managed Flow control Half-Duplex Flow controlIeee 802.3 Ethernet Frame Ethernet Interface PortRegisters Related to the Ethernet Port DTE and DCE ModeConfigured as DTE Connected to an Ethernet PHY in MII Mode DS33Z41 Configured as a DCE in MII Mode Address Register Description Ethernet MACMAC Control Registers MAC Status RegistersRmii Mode MII ModePHY MII Management Block and Mdio Interface Bert FeaturesBert Prbs Synchronization Receive Data InterfaceRepetitive Pattern Synchronization Receive Pattern DetectionPattern Generation Error InsertionPattern Monitoring Performance Monitoring Update Transmit Packet Processor Receive Packet Processor Page 14. Laps Encoding of MAC Frames Concept 18 X.86 Encoding and Decoding15. X.86 Encapsulation of the MAC field Page Committed Information Rate Controller 16. CIR in the WAN Transmit Path Bert Device RegistersRegister Address Map Name Register Bit MapsGlobal Register Bit Map Global Register Bit MapBert Register Bit Map Arbiter Register Bit MapBert Register Bit Map Arbiter Register Bit MapSerial Interface Register Bit Map Serial Interface Register Bit MapRepie Rapie Ripdie Rspdie Rlpdie Repcie Rapcie Rspcie RMX15 RMX14 RMX13 RMX12 RMX11 RMX10 RMX9 RMX8Repc Rapc Rspc Repl Rapl Ripdl Rspdl Rlpdl Repcl Rapcl RspclEthernet Interface Register Bit Map Ethernet Interface Register Bit MapMAC Register Bit Map MAC Indirect Register Bit Map200h GL.IDRH Global Register DefinitionsGL.IDRL GL.BLR GL.CR1Global Sdram Reference Clock Activity Latched Status GL.RTCAL04h GL.SRCALSGL.SIS GL.LIEGL.LIS GL.SIEGL.IBIS GL.TRQIEGL.TRQIS GL.IBIEGL.C1QPR GL.CON1GL.IMXC Available User Commands Value CommentGL.IMXCN GL.IMXSIE GL.IMXSSGL.IMXDFDELS GL.IMXSLSGL.IMXDFD GL.IMXDFEIE1Eh Inverse MUX OOF Interrupt EnableGL.IMXOOFIE GL.BISTPF GL.IMXOOFLSGL.BISTEN GL.SDMODEWS GL.SDMODE1GL.SDMODE2 SREFT7 SREFT6 SREFT5 SREFT4 SREFT3 SREFT2 SREFT1 SREFT0 GL.SDRFTCGlobal Sdram Refresh Time Control 3DhAR.TQSC1 Arbiter RegistersArbiter Register Bit Descriptions AR.RQSC1Bit 7 This bit must be kept low for proper operation Bert RegistersBert Control Register 80h83h Bert Pattern Configuration Low RegisterBert Pattern Configuration High Register 82h85h Bert Pattern Byte 0 Register84h Bert Pattern Byte 1 Register8Ch Transmit Error Insertion Control Register88h Bert Status Register90h Bert Status Register Interrupt EnableBert Status Register Latched 8EhRBECR2 9Ah Receive Bit Count Byte 1 Register #199h Receive Bit Count Byte 2 RegisterLI.RSTPD Serial Interface RegistersSerial Interface Transmit and Common Registers Serial Interface Transmit Register Bit Descriptions0C4h Transmit Hdlc Processor RegistersLI.TPPCL Transmit Packet Processor Control Low RegisterLI.TEPLC LI.TIFGC0C7h Transmit Errored Packet High Control RegisterCleanup routine LI.TEPHCLI.TPPSRIE LI.TPPSRLI.TPPSRL LI.TPCR2 LI.TPCR0LI.TPCR1 LI.TBCR3 LI.TBCR0LI.TBCR1 LI.TBCR2LI.THPMUS LI.THPMUULI.TRX8C 4 X.86 RegistersLI.TX86EDE LI.TRX86ALI.CIR LI.TRX86SAPILLI.RMPSCL Receive Serial InterfaceLI.RPPCL LI.RPPSR LI.RMPSCH105h LI.RPPSRLReceive Packet Processor Status Register Latched 106h Receive Packet Processor Status Register Interrupt EnableLI.RPPSRIE LI.RPCB2 LI.RPCB0LI.RPCB1 LI.RFPCB2 LI.RFPCB0LI.RFPCB1 LI.RAPCB2 LI.RAPCB0LI.RAPCB1 LI.RSPCB2 LI.RSPCB0LI.RSPCB1 LI.RBC3 LI.RBC0LI.RBC1 LI.RBC2LI.RAC3 LI.RAC0LI.RAC1 LI.RAC2LI.RX86S LI.RHPMUULI.RHPMUS LI.TQLT LI.RX86LSIELI.TQCTLS LI.TQHTLI.TQTIE SU.MACRADH Ethernet Interface RegistersEthernet Interface Register Bit Descriptions SU.MACRADLSU.MACWD0 SU.MACRD1SU.MACRD2 SU.MACRD3SU.MACAWL SU.MACWD1SU.MACWD2 SU.MACWD3SU.MACRWC SU.MACAWHSU.GCR SU.LPBKNcfq Tprhbc Tprcb SU.TFRCTransmit Frame Resend Control 151hSU.TFSH SU.TFSLSU.RFSB2 SU.RFSB0SU.RFSB1 MCF SU.RFSB3157h SU.RQHT SU.RMFSRLSU.RMFSRH SU.RQLTSU.QCRLS SU.QRIEUcfr Cfrr Lerr Crcerr DBR Miier BFR SU.RFRCReceive Frame Rejection Control 15EhSU.MACCR MAC RegistersBit Random Number Generator Bits Used SU.MACAL SU.MACAHSU.MACMIIA SU.MACMIID SU.MACFCR SU.MMCCTRL 010Eh MAC Reserved Control Register010Ch indirect 010Dh0113h 0110h indirect0111h 0112h0201h SU.RxFrmCtrMAC All Frames Received Counter 0200h indirect0205h SU.RxFrmOkCtrMAC Frames Received OK Counter 0204h indirect0301h SU.TxFrmCtrMAC All Frames Transmitted Counter 0300h indirect0309h SU.TxBytesCtrMAC All Bytes Transmitted Counter 0308h indirect030Dh SU.TxBytesOkCtrMAC Bytes Transmitted OK Counter 030Ch indirectSU.TXFRMUNDR 0339h SU.TxBdFrmCtrMAC All Frames Aborted Counter 0338h indirectMII and Rmii Interfaces Functional TimingMII Receive Functional Timing Recommended DC Operating Conditions DC Electrical CharacteristicsParameter Symbol Conditions MIN TYP MAX Units Operating ParametersAIR Flow THETA-JA Thermal Characteristics -3. Thermal CharacteristicsTheta-JA vs. Airflow Parameter MIN TYP MAXMIN TYP MAX Parameter SymbolMII Interface Transmit MII Interface 10Mbps 100MbpsReceive MII Interface Timing Receive MII InterfaceRmii Interface Transmit Rmii Interface Receive Rmii Interface Timing Receive Rmii InterfaceMDC Mdio Parameter Symbol MIN TYP MAX UnitsMdio Interface -9. Mdio Interface Tclki Tser Tsync Transmit WAN Interface 10. Transmit WAN InterfaceRclki Rser Rsync Receive WAN Interface 11. Receive WAN InterfaceSdclko to SRAS, SCAS, SWE, Sdcs Sdram Timing 12. Sdram Interface Timing100MHz SRAS, Scas SdataBIT Level Detail Rclki Rsync Link #1, Channel #1 Rsync Rser10. Transmit IBO Channel Interleave Mode Timing VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8 ± 5% Tj = -40C to +85C 11. Intel Bus Read Timing Modec = 13. Motorola Bus Read Timing Modec = Jtag Interface Timing 14. Jtag Interface Timing 15. Jtag Interface Timing DiagramJtag Information Jtag Functional Block DiagramJtag TAP Controller State Machine Description Capture-IR Instruction Register TAP Controller State DiagramInstruction Codes for Ieee 1149.1 Architecture Bypass Register Jtag ID Codes ID Code StructureTest Registers Boundary Scan RegisterJtag Functional Timing 13.1 169-Ball CSBGA, 14mm x 14mm 56-G6035-001 Package InformationRevision Description Document Revision History

MAC Reserved Control Register

010Ch (indirect)

010Dh:

010Eh:

010Fh: