DS33Z41 Quad IMUX Ethernet Mapper
Register Name: |
| BSRL |
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Register Description: |
| BERT Status Register Latched |
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Register Address: |
| 8Eh |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Name | — | — |
| — | — | PMSL | BEL | BECL | OOSL |
Default | — | — |
| — | — | — | — | — | — |
Bit 3: Performance Monitor Update Status Latched (PMSL). This bit is set when the PMS bit transitions from 0 to 1.
Bit 2: Bit Error Detected Latched (BEL). This bit is set when a bit error is detected.
Bit 1: Bit Error Count Latched (BECL). This bit is set when the BEC bit transitions from 0 to 1.
Bit 0: Out Of Synchronization Latched (OOSL). This bit is set when the OOS bit changes state.
Register Name: |
| BSRIE |
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Register Description: |
| BERT Status Register Interrupt Enable |
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Register Address: |
| 90h |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Name | — | — |
| — | — | PMSIE | BEIE | BECIE | OOSIE |
Default | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 |
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit enables an interrupt if the PMSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Bit Error Interrupt Enable (BEIE). This bit enables an interrupt if the BEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit enables an interrupt if the BECL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the OOSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
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