Maxim DS33Z41 specifications PHY MII Management Block and Mdio Interface, Bert Features

DS33Z41 Quad IMUX Ethernet Mapper

8.14.3 PHY MII Management Block and MDIO Interface

The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management Interface is shown Figure 8-11. The read/write control of the MII Management is accomplished through the indirect SU.MACMIIA MII Management Address Register and data is passed through the indirect SU.MACMIID Data Register. These indirect registers are accessed through the MAC Control Registers defined in Table 8-8. The MDC clock is internally generated and runs at 1.67MHz. Note that the DS33Z41 provides a single MII Management port, and all control registers for this function are located in MAC 1.

Figure 8-11. MII Management Frame

	Preamble	Start	Opco	Phy Adrs	Phy Reg	Turn	Data	Idle
						Aroun
			de
						d	16	1
	32 bits	2 bits	2 bits	5 bits	5 bits
						2 bits	bits	Bit
READ	111...111	01	10	PHYA[4:0]	PHYR[4:0]	ZZ	ZZZZZZZZZ	Z
WRITE	111...111	01	01	PHYA[4:0]	PHYR[4:0]	10	PHYD[15:0]	Z

8.15 BERT

The BERT can be used for generation and detection of BERT patterns. The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. The following restrictions are related to the BERT:

•The user should provide a gapped clock on RCLKI and TCLKI that is active during channels in which the user wishes to insert the BERT pattern. Several of the Dallas Semiconductor Framers and Transceivers provide programmable channel blocking pins for this purpose.

•BERT will transmit even when the device is set for X.86 mode.

•The normal traffic flow is halted while the BERT is in operation.

•If the BERT is enabled for a Serial port, it will override the normal connection.

•If there is a connection overridden by the BERT, when BERT operation is terminated the normal operation is restored.

The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern.

8.15.1 BERT Features

•PRBS and QRSS patterns of 29-1, 215-1, 223-1, and QRSS pattern support.

•Programmable repetitive pattern. The repetitive pattern length and pattern are programmable (length n = 1 to 32 and pattern = 0 to (2n – 1).

•24-bit error count and 32-bit bit count registers.

•Programmable bit error insertion. Errors can be inserted individually.

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