2 Troubleshooting Procedures | 2.4 System Board Troubleshooting |
Table
LED Status | Test item | Message |
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00h | Prohibition of cache |
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| Permission of L1/L2 cache in |
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| FlashROM area |
|
| Initialization of H/W (before | Initialization of MCH |
| DRAM recognition) |
|
|
| Initialization of ICH.D30.Func0 |
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|
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| Initialization of ICH.D31.Func0 |
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|
|
|
| Initialization of ICH.D31.Func1/2 |
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| Initialization of USB Controller |
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|
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| Initialization of ICH.D31.Func3 |
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| Initialization of ICH Audio |
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| Initialization of TI Controller |
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|
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| Initialization of PIT channel 1 | (Setting the refresh interval to “30∝s”) |
|
|
|
01h | Check of DRAM type and size | When unsupported memory is connected, becoming |
| (at cold boot) | HLT after beep sound |
|
|
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| HLT when DRAM size is 0 | |
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| HLT When it can not be used as a stack |
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|
|
02h | Cache configuration |
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| Cache permission |
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|
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| CMOS access test | (HLT when an error is detected) |
| (at cold boot) |
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|
|
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| Battery level check of CMOS |
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| CMOS checksum check |
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|
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| Initialization of CMOS data (1) |
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|
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| Setting of IRT status | (Setting of boot status and IRT busy flag, The rest bits |
|
| are 0) |
| Storing DRAM size in CMOS |
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|
|
|
03h | Resume branch (at cold boot) | Not resume when a CMOS error occurred |
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| Not resume when resume status code is not set |
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| Resume error check |
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| S3 returning error (1CH) (Resume error LED=7AH) |
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| |
|
| LED=73H) |
|
| Check of memory configuration change (Resume |
|
| error LED=73H) |
|
| RAM area checksum check in system BIOS |
|
| (Resume error LED=79H) |
[CONFIDENTIAL] | TECRA S3 Maintenance Manual |