Address | Chip in Use |
C00 | PCI IRQ mapping index register |
|
|
C01 | PCI IRQ mapping data register |
|
|
C14 | PCI error status register |
|
|
C49 | Address & status control |
|
|
C4A | Rise time counter control |
|
|
C52 | General register (GPMs) |
|
|
C6C | ISA wait register |
|
|
C6F | Other control registers |
|
|
CA2 - CA3 | IPMI (MPI KCS interface) |
|
|
CA4 - CA5 | IPMI (SMI interface) |
|
|
CA6 - CA7 | IPMI (SCI/SW1 interface) |
|
|
CD6 | Power management index register |
|
|
CD7 | Power management data register |
|
|
CF8, CFC | PCI configuration space |
|
|
CF9 | Reset control |
|
|
F50 - F58 | General chipset |
FE00 - FE3F | Chipset |
BAR4+00 - 0F | EDMA2 PCI base address register 4 |
*1 Hexadecimal notation
*2 The I/O port address of a PCI device is set according to its type and number.
