External Bus Interface Operation | Motorola MC68340 specification

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NOTE

If an access matches multiple chip selects, the lowest numbered chip select will have priority. For example, if CS0 and CS2 "overlap" for a certain range, CS0 will assert when accessing the "overlapped" address range, and CS2 will not.

Global chip select provides a 16-bit port with three wait states, which allows a boot ROM to be located in any address space and still provide the stack pointer and program counter values at $00000000 and $00000004, respectively. Global chip select does not provide write protection and responds to all function codes. While CS0 is a global chip select, no other chip select (CS1, CS2, CS3) can be used. CS0 operates in this manner until the V-bit is set in the CS0 base address register, which will then allow the use of CS3–CS1. Provided the desired address range is first loaded into the CS0 base address register, CS0 can be programmed to continue decode for a range of addresses after the V-bit is set, After the V-bit is set for CS0, global chip select can only be restarted with a system reset.

Asystem can use an 8-bit boot ROM if an external 8-bit DSACK≈ that responds in two or less wait states is generated. The 8-bit DSACK≈ must respond in two or less wait states so that the global chip select, which responds with three wait states, will not be used. See Section 10 Applications for a detailed discussion.

4.2.5 External Bus Interface Operation

This section describes port A and port B functions. Refer to Section 3 Bus Operation for more information about the EBI.

4.2.5.1PORT A. Port A pins can be independently programmed to function as either addresses A31–A24, discrete I/O pins, or IACKx pins. The port A pin assignment registers (PPARA1 and PPARA2) control the function of the port A pins as listed in Table 4-4. Upon reset, port A is configured as input pins. If the system uses these signals as addresses, pulldowns should be put on these signals to avoid indeterminate values until the port A registers can be programmed.

Table 4-4. Port A Pin Assignment Register

		Pin Function
Signal	PPARA1 = 0	PPARA1 = 1	PPARA1 = 0
	PPARA2 = 0	PPARA2 = X	PPARA2 = 1
A31	A31	PORT A7	IACK7
A30	A30	PORT A6	IACK6
A29	A29	PORT A5	IACK5
A28	A28	PORT A4	IACK4
A27	A27	PORT A3	IACK3
A26	A26	PORT A2	IACK2
A25	A25	PORT A1	IACK1
A24	A24	PORT A0	—

MOTOROLAMC68340 USER’S MANUAL4- 15

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola MC68340 manual External Bus Interface Operation, Port a Pin Assignment Register

Models: MC68340

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

4.2.5 External Bus Interface Operation

Table 4-4. Port A Pin Assignment Register

Pin Function

Signal

PPARA1 = 0

PPARA2 = 0

PPARA2 = X

MC68340 specifications