Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

Table 5-2. Instruction Set Summary

Opcode

Operation

 

Syntax

ABCD

Source 10 + Destination10 + X ⇒ Destination

ABCD Dy,Dx

 

 

 

ABCD –(Ay),–(Ax)

ADD

Source + Destination ⇒ Destination

ADD 〈 ea〉,Dn

 

 

 

ADD Dn,〈 ea〉

ADDA

Source + Destination ⇒ Destination

ADDA 〈ea〉,An

ADDI

Immediate Data + Destination ⇒

Destination

ADDI #〈 data〉,〈 ea〉

ADDQ

Immediate Data + Destination ⇒

Destination

ADDQ # 〈data 〉,〈ea〉

ADDX

Source + Destination + X ⇒ Destination

ADDX Dy,Dx

 

 

 

ADDX –(Ay),–(Ax)

AND

Source Λ Destination ⇒ Destination

AND 〈 ea〉, Dn

 

 

 

AND Dn,〈 ea〉

ANDI

Immediate Data Λ Destination ⇒ Destination

ANDI #〈 data〉,〈 ea〉

ANDI to CCR

Source Λ CCR ⇒ CCR

 

ANDI #〈 data〉 ,CCR

ANDI to SR

If supervisor state

 

ANDI #〈 data〉,SR

 

the Source Λ SR ⇒ SR

 

 

 

else TRAP

 

 

ASL,ASR

Destination Shifted by 〈 count〉 ⇒ Destination

ASd Dx,Dy

 

 

 

ASd # 〈data 〉,Dy

 

 

 

ASd 〈ea〉

Bcc

If (condition true) then PC + d ⇒ PC

Bcc 〈label〉

BCHG

~(〈number 〉 of Destination) ⇒ Z;

 

BCHG Dn,〈 ea〉

 

~(〈number 〉 of Destination) ⇒ 〈bit number〉 of

BCHG # 〈data 〉,〈ea〉

 

Destination

 

 

BCLR

~(〈number 〉 of Destination) ⇒ Z;

 

BCLR Dn, 〈ea〉

 

0 ⇒ 〈bit number〉 of Destination

 

BCLR # 〈data 〉,〈ea〉

BGND

If (background mode enabled) then

BGND

 

enter background mode

 

 

 

else Format/Vector offset ⇒ –(SSP)

 

 

PC ⇒ –(SSP)

 

 

 

SR ⇒ –(SSP)

 

 

 

(Vector) ⇒ PC

 

 

BKPT

Run breakpoint acknowledge cycle;

BKPT #〈 data〉

 

TRAP as illegal instruction

 

 

BRA

PC + d ⇒ PC

 

BRA 〈 label〉

BSET

~(〈number 〉 of Destination) ⇒ Z;

 

BSET Dn,〈 ea〉

 

1 ⇒ 〈bit number〉 of Destination

 

BSET #〈 data〉,〈 ea〉

BSR

SP – 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC

BSR 〈 label〉

BTST

– (〈number 〉 of Destination) ⇒ Z;

 

BTST Dn, 〈ea〉

 

 

 

BTST # 〈data 〉,〈ea〉

CHK

If Dn < 0 or Dn > Source then TRAP

CHK 〈 ea〉,Dn

CHK2

If Rn < lower bound or

 

CHK2 〈ea〉,Rn

 

If Rn > upper bound

 

 

 

then TRAP

 

 

CLR

0 ⇒ Destination

 

CLR 〈 ea〉

CMP

Destination — Source ⇒ cc

 

CMP 〈 ea〉,Dn

CMPA

Destination — Source

 

CMPA 〈 ea〉,An

CMPI

Destination — Immediate Data

 

CMPI # 〈data〉,〈 ea〉

CMPM

Destination — Source ⇒ cc

 

CMPM (Ay)+,(Ax)+

5- 16MC68340 USER’S MANUALMOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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Motorola MC68340 manual Instruction Set Summary, Opcode Operation Syntax
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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