Motorola MC68340 manual DMA Channel Operation, Channel Initialization and Startup

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

6.5 BUS ARBITRATION

The DMA controller module uses the M68000 bus arbitration protocol to request bus mastership for DMA transfers. Each channel arbitrates for the bus independently. The source (read) DMA bus cycle has timing identical to a read bus cycle. The destination (write) DMA bus cycle has timing identical to a write bus cycle. However, the DMA channel transfers are unique in one respect—FC3 can be asserted during the source operand bus cycle and remain asserted until the end of the destination operand bus cycle.

For internal request generation as soon as the CCR STR bit is set, the DMA channel arbitrates for the bus and begins to transfer data when it becomes bus master. For external request generation, the STR bit must be set and a DREQ≈ signal must be asserted before the channel arbitrates for the bus and begins a transfer.

6.6 DMA CHANNEL OPERATION

The following paragraphs describe the programmable channel functions available for the DMA channel, the data transfer operations, and behavior during cycle termination. This description applies to both channels.

Any DMA channel operation adheres to the following basic sequence:

1.Channel Initialization and Startup—The channel registers are initialized. The channel is then started by setting the CCR STR bit. The first operand transfer request (either internally or externally generated) is recognized.

2.Data Transfer—After a channel is started, it transfers one operand in response to each request until an entire data block is transferred.

3.Channel Termination—The channel can terminate by normal completion or from an error. The channel status register (CSR) indicates the status of the operation.

6.6.1 Channel Initialization and Startup

Before starting a block transfer operation, the channel registers must be initialized with information describing the channel configuration, request generation method, and data block. This initialization is accomplished by programming the appropriate information into the channel registers.

The SAR is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to a peripheral device or memory to memory, the source address is the starting address of the data block. This address may be any byte address. In the single-address mode with the destination (write) device requesting mode of operation, this register is not used.

The DAR should contain the destination (write) address. If the transfer is from a peripheral device to memory or memory to memory, the DAR is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, the DAR is loaded with the address of the peripheral data register. This address may be any byte

6- 18MC68340 USER’S MANUALMOTOROLA

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