Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Fetch Effective Address Instruction Timing Table, 5-99

FFULL Bit, 7-25

FFULLA Signal, 7-7

Fill Memory Block Command, 5-82

FIRQ Bit, 4-5, 4-16, 4-22, 4-35–4-36

FORCE_BGND, 5-72

Format Error Exception, 5-47, 5-52

Four-Word Stack Frame, 5-51, 5-60

Framing Error, 7-11, 7-24

Freeze Operation, 4-17, 6-24, 7-20, 8-19

FREEZE Signal, 2-10, 4-3, 4-17, 4-22–4-23, 4-36,

5-66–5-68, 5-71–5-72

Frequency Adjusted Signal

Skew, 10-9

Width, 10-8

Frequency Divider, 4-12

FRZ Bits, 4-17–4-18, 4-21–4-22, 4-36, 6-24, 7-20,

7-46, 8-19, 8-27,

FTE Bit, 4-14, 4-30

Full Format Instruction Word,

Function Code, 3, 6-18, 6-32

Encoding, 2-5, 3-3

Register, 6-7, 6-10, 6-12, 6-15, 6-32, 6-38, 6-37

Signals, 2-5, 3-2, 3-17

— G —

Global Chip Select, 4-14–4-15, 4-36

GO Command, 5-68, 5-83–5-84

— H —

Halt

Operation, 3-38, 3-39, 3-41

Signal, 2-8, 3-4, 3-13–3-15, 3-30, 3-32–3-38,

4-4, 4-6, 4-17

Halted Processing State,

Halted Processor Causes, 3-40

Hardware Breakpoints, 5-60, 5-64–5-65

— I —

IACK Signals, 4-15, 4-34

IARB Bits, 4-5, 4-22, 4-36, 6-25–6-26, 6-36, 7-21, 7-46, 8-19, 8-27

ICCS Bit, 7-20, 7-46

IE Bits, 8-4, 8-8–8-9, 8-21, 8-27 IEC Bits, 7-32, 7-46

IEEE 1149.1, 4-2, 9-1 Capabilities, 9-1, 9-4 Implementation, 9-2 Block Diagram, 9-2 Instruction Encoding, 9-10 Control Bits, 9-4 Restrictions, 9-11

IFETCH Signal, 5-64, 5-68–5-69, 5-87–5-88

IL Bits, 7-21, 7-46, 8-20, 8-27 IMB, 6-19, 7-1, 8-1

Immediate Arithmetic/Logical Instruction Timing Table, 5-105

IN Bit, 5-53, 5-56, 5-61 Input Port, 7-35

Change Register, 7-31 Instruction

Cycles, 5-97

Execution Overlap, 5-91–5-92, 5-94–5-95 Execution Time Calculation, 5-92–5-93 Fetch Signal, 2-19

Heads, 5-91–5-94, 5-97 Pipe Signal, 2-10

Pipeline Operation, 5-89–5-90, 5-93 Register, 9-9–9-10

Stream Timing Examples, 5-94–5-97 Tails, 5-91–5-94, 5-97

Timing Table Overview, 5-97–5-98 INTB Bit, 6-20, 6-27, 6-36

INTE Bit, 6-20, 6-27, 6-36

Integer Arithmetic Operations, 5-46–5-47 Internal

Autovector, 3-4, 3-29, 4-23, 4-36 Bus Arbitration, 6-18

Bus Masters, 4-6, 6-25

Bus Monitor, 3-4, 3-32, 4-4, 4-6, 4-17 Data Multiplexer, 3-7

DMA Request, 6-2, 6-4, 6-5

DSACK signals, 3-5, 3-13–3-14, 3-28, 4-2, 4-4, 4-14–4-15, 4-32

Exceptions, 5-66 Interrupt

Acknowledge Arbitration, 4-6, 6-25–6-26, 7-17 Acknowledge Cycle Types, 3-27

Autovector, 3-29 Autovector, Timing, 3-31 Flowchart, 3-28 Terminated Normally, 3-27, 4-7 Timing, 3-29

Acknowledge Cycle, 3-27

Acknowledge Signals, 3-29 Arbitration, 4-5–4-6, 7-21 Enable Register, 7-4, 7-34, 7-46 Exception, 5-68–5-69

Level Register, 7-21, 7-46

Register, 6-26, 8-20, 8-27

Request Signals, 2-5–2-6, 3-27–3-28, 6-26, 7-3, 7-21, 7-34, 8-4, 8-8, 8-9, 8-20

Status Register, 7-4, 7-22, 7-32, 7-34, 7-46 Vector Register, 7-4, 7-17, 7-21, 7-46

INTL Bits, 6-26, 6-36

INTN Bit, 6-27, 6-36

INTV Bits, 6-26, 6-36

IPIPE Signal, 5-87–5-88, 5-64, 5-68–5-69 IRQ Bit, 6-20, 6-31, 8-23

ISM Bits, 6-25, 6-36

IVR Bits, 7-22, 8-20, 8-27

Index-4

MC68340 USER’S MANUAL

MOTOROLA

 

For More Information On This Product,

 

 

Go to: www.freescale.com

 

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Motorola MC68340 manual Index-4
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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