Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

6.4.2 Dual-Address Mode

The dual-address DMA bus cycle transfers data between a device or memory and the DMA internal holding register (DHR). In this mode, any operand transfer takes place in two DMA bus cycles, one where a device is addressed and one where memory is addressed. The data transferred during a dual-address operation is either read from the data bus into the DHR or written from the DHR to the data bus.

Each DMA channel can each be programmed to operate in the dual-address transfer mode. In this mode, the operand is read from the source address specified in the SAR and placed in the DHR. The operand read may take up to four bus cycles to complete because of differences in operand sizes of the source and destination. The operand is then written to the address specified in the DAR. This transfer may also be up to four bus cycles long. In this manner, various combinations of peripheral, memory, and operand sizes may be used. See 6.7 Register Description for more information.

The dual-address transfers can be started by either the internal request mode or by an external device using the DREQ≈ input signal. When the external device uses DREQ≈, the channel can be programmed to operate in either burst transfer mode or cycle steal mode.

6.4.2.1DUAL-ADDRESS READ. During the dual-address read cycle, the DMA reads data from a device or memory into the internal DHR. The device or memory is selected by the address specified in the SAR, the source function codes in the FCR, and the source size in the CCR. Data is read from the memory or peripheral and placed in the DHR when the bus cycle is terminated. When the complete operand has been read, the SAR is

incremented by 0, 1, 2, or 4, according to the size and increment information specified by the SSIZE and SAPI bits of the CCR. The DMA control signals (DACK≈ and DONE≈) are asserted in the source (read) cycle when the source device makes a request. See Figures 6-9 and 6-10 for timing diagrams of dual-address read for external burst and cycle steal modes.

6- 12MC68340 USER’S MANUALMOTOROLA

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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