Single-Address Read Timing Cycle Steal | Motorola MC68340 guide

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

DMA READ

S4

S2

S0

CYCLE

S4

CPU

S2

S0

READ

S4

DMA

S2

S0

CYCLE

S4

S2

CPU

S0

CPU CYCLE

S2 S4

S0

CLKOUT

A31–A0

FC3–FC0

SIZ1–SIZ0

AS

DS

R/W

D15–D0

DSACKx

DREQx

DONEx

(INPUT)

DACKx

DONEx

(OUTPUT)

NOTE:

clocks for a DMA request to be recognized.		asserted after DACKx is asserted and before DACKx is negated.




for two consecutive		transfer, DREQx is


DREQx must be active		To cause another DMA
1.	2.

3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.

Figure 6-6. Single-Address Read Timing (Cycle Steal)

MOTOROLAMC68340 USER’S MANUAL6- 9

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Motorola MC68340 manual Single-Address Read Timing Cycle Steal

MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Contents

Freescale Semiconductor, Inc MC68340 Freescale Semiconductor, Inc CPU32 Preface Table of Contents Table of Contents Section Bus Operation 15.4 Section System Integration Module Section U 3 Pipeline Synchronization with the NOP Instruction 3.1 Types of Faults 3.1.1 Type I-Released Write Faults 3.1.2 2.4 Command Execution 2.5 Section DMA Controller Module Section Serial Module OP1 RtsaOP0 Rtsb 1.4 Clock Selection Logic Section Timer Modules Section Applications Section Ieee 1149.1 Test Access Port Table of Contents Concluded List of Illustrations List of Illustrations External and Internal Interface Signals 10-1 Minimum System Configuration Block Diagram 10-2 Xxi List of Illustrations Concluded B l e List of Tables List of Tables Section Device Overview M68300 Family Advantages Freescale Semiconductor, Inc OrganizationCentral Processor Unit Freescale Semiconductor, Inc 1 CPU32 Background Debug Mode System Integration Module ON-CHIP Peripherals 6MC68340 USER’S Manualmotorola Serial Module Direct Memory Access Module Power Consumption Management Timer Modules Compact DISC-INTERACTIVE Physical Document Number Document Name More Information Section Signal Descriptions Input Signal IndexSignal Index Signal Name Mnemonic Function Output CTSA, Ctsb Data BUS D15-D0 Address BUSAddress Bus A23-A0 Address Bus A31-A24 Function Code Bits Address Spaces Function Codes FC3-FC0Chip Selects CS3-CS0 Address Space Encoding Address Strobe AS BUS Control SignalsInterrupt Request Level IRQ7, IRQ6, IRQ5, IRQ3 Data and Size Acknowledge DSACK1, DSACK0 BUS Arbitration Signals Clock Signals Exception Control Signals Instrumentation and Emulation Signals DMA Module Signals Serial Module Signals Timer Output TOUT2, TOUT1 Timer SignalsTimer Gate TGATE2, TGATE1 Timer Input TIN2, TIN1 Signal Summary Test SignalsSynthesizer Power Vccsyn System Power and Ground VCC and GND Signal Name Mnemonic Input/Output Active State Signal Summary DACK2, DACK1 Section BUS Operation BUS Transfer Signals Input Sample Window Bus Control Signals Function Code Signals Freescale Semiconductor, Inc Address Bus A31-A0 Bus Cycle Termination Signals Dynamic Bus Sizing Data Transfer Mechanism 6MC68340 USER’S Manualmotorola Operand Transfer Cases Misaligned Operands OP0 Data BUS OP0 OP1 Data BUS Semiconductor Long-Word Operand Read Timing from 8-Bit Port Long-Word Operand Write Timing to 8-Bit Port Long-Word and Word Read and Write Timing-16-Bit Port Synchronous Operation with DSACK≈ Freescale Semiconductor, Inc Bus Operation Fast Termination Timing Fast Termination Cycles Read Cycle Data Transfer Cycles MOTOROLAMC68340 USER’S MANUAL3 Freescale Semiconductor, Inc Write Cycle Word Write Cycle Flowchart Read-Modify-Write Cycle Timing Read-Modify-Write Cycle 20MC68340 USER’S Manualmotorola 10. CPU Space Address Encoding CPU Space Cycles Freescale Semiconductor, Inc Breakpoint Acknowledge Cycle Freescale Semiconductor, Inc Lpstop Broadcast Cycle 11. Breakpoint Operation Flowchart 12. Breakpoint Acknowledge Cycle Timing Opcode Returned 13. Breakpoint Acknowledge Cycle Timing Exception Signaled Interrupt Acknowledge Bus Cycles 14. Interrupt Acknowledge Cycle Flowchart FC3-FC0 CPU Space SIZ0 Byte SIZ1 30MC68340 USER’S Manualmotorola 16. Autovector Operation Timing BUS Exception Control Cycles Control Signal ResultDSACK≈, BERR, and Halt Assertion Results Asserted on Rising Edge of State Freescale Semiconductor, Inc Bus Errors 17. Bus Error without DSACK≈ Retry Operation 18. Late Bus Error with DSACK≈ 19. Retry Sequence 20. Late Retry Sequence Halt Operation 21. Halt Timing Double Bus Fault BUS Arbitration 22. Bus Arbitration Flowchart for Single Request 23. Bus Arbitration Timing Diagram-Idle Bus Case Bus Grant Freescale Semiconductor, Inc Bus RequestBus Grant Acknowledge Show Cycles Freescale Semiconductor, Inc Bus Arbitration Control 25. Bus Arbitration State Diagram 26. Show Cycle Timing Diagram Reset Operation Semiconductor 28. Power-Up Reset Timing Diagram Module Overview Section System Integration Module Module Base Address Register Operation Module Operation SIM40 Module Register Block System Configuration and Protection Operation 4MC68340 USER’S Manualmotorola System Configuration and Protection Function 6MC68340 USER’S Manualmotorola Software Watchdog Block Diagram Periodic interrupt timer period Pitr count value Operating Mode DescriptionClock Synthesizer Operation Clock Operating Modes Clock Block Diagram for Crystal Operation Clock Block Diagram for External Oscillator Operation Fvco = Fsystem = 0 X = = 1 X = Clock Control SignalsChip Select Operation System Frequencies from 32.768-kHz Reference 14MC68340 USER’S Manualmotorola External Bus Interface Operation Pin Function Signal PPARA1 = PPARA2 =Port a Pin Assignment Register Pparb = Pin Function Signal Firq = Freeze Low-Power Stop Programming Model SIM40 Programming Model Mbar MCR System Configuration and Protection Registers SHEN1 SHEN0 Action SHENx Control Bits RSR Sypcr SwivSee 4.2.2.5 Software Watchdog for more information MHz External Deriving Software Watchdog TimeoutSoftware Timeout Period Crystal Period Clock Period For more information see 4.2.2.2 Internal Bus Monitor Interrupts by Sources in the SIM40 for the servicing order BMTx EncodingPicr Pirql Encoding Pitr Syncr Clock Synthesizer Control Register Syncr Chip Select Registers Base Address $046, $04E, $056, $05E Address Mask $042, $04A, $052, $05A Mode 10. DDx Encoding11. PSx Encoding Response External Bus Interface Control Porta PORTB, PORTB1 $01F MC68340 Initialization Sequence 2 SIM40 Module ConfigurationStartup Freescale Semiconductor, Inc MCR EQU Sspinit EQUMbar EQU Modbase EQU $FFFFF000 MOVES.L D0,MBAR MOVEQ.LMOVEC.L D0,DFC MOVE.L #MODBASE+1,D0 END CSAM0$ DC.L $0001FFFD Overview Section CPU32 Virtual Memory Freescale Semiconductor, Inc Features CPU32 Block Diagram Loop Mode Instruction Execution Exception Handling Vector Base Register CAS, CAS2 Freescale Semiconductor, Inc Addressing ModesInstruction Set BFFFO, BFINS, BFSET, Bftst Mnemonic Description Instruction Set Privilege States Processing States Programming Model Architecture Summary User Programming Model Status Register Freescale Semiconductor, Inc Registers 1 M68000 Family Compatibility Instruction SET Instruction Word General Format Instruction Format and Notation Example d 16 is a 16-bit displacement DFC CCRSSP USP Freescale Semiconductor, Inc Instruction Summary Opcode Operation Syntax Instruction Set Summary Extb Llegal Opcode Operation Source ⇒ Destination Movep Dx,d,Ay Movep d,Ay,Dx ROXL,ROXR Instruction Set Summary Concluded Operations Special Definition Condition Code Computations Instruction Syntax Data Movement Operations 22MC68340 USER’S Manualmotorola DIVS/DIVU Integer Arithmetic Operations Logic Operations Bit Manipulation Operations Shift and Rotate Operations Unconditional Binary-Coded Decimal Operations10. Program Control Operations Conditional Freescale Semiconductor, Inc Condition Code Register 11. System Control OperationsPrivileged Trap Generating 12. Condition Tests Using the TBL InstructionsMnemonic Condition Encoding Entry Number Value 13. Standard Usage Entries Table Example 2 Compressed TABLE. In Example 2 see -8, 14. Compressed Table Entries Subroutine Instruction Table Example 15 -Bit Independent Variable Entries Following value has been calculated for independent variable Summing, the following result is obtained Pipeline Synchronization with the NOP Instruction Nested Subroutine CallsProcessing States Privilege Levels Freescale Semiconductor, Inc State Transitions Exception Processing Assignment Freescale Semiconductor, Inc Exception Vectors16. Exception Vector Assignments Vector Number Dec Hex 40MC68340 USER’S Manualmotorola 10. Exception Stack Frame Characteristics Group Exception Priority Relative Priority Reset17. Exception Priority Groups Freescale Semiconductor, Inc 11. Reset Operation Flowchart Freescale Semiconductor, Inc 46MC68340 USER’S Manualmotorola Freescale Semiconductor, Inc Lpstop Reset RTE StopMove USP Movec Moves Tracing Function 18. Tracing Control 50MC68340 USER’S Manualmotorola Freescale Semiconductor, Inc Fault Recovery Freescale Semiconductor, Inc 54MC68340 USER’S Manualmotorola SIZ Func 56MC68340 USER’S Manualmotorola Freescale Semiconductor, Inc 58MC68340 USER’S Manualmotorola Freescale Semiconductor, Inc 12. Format $0-Four-Word Stack Frame Freescale Semiconductor, Inc 4 CPU32 Stack Frames 14. Internal Transfer Count Register 15. Format $C-BERR Stack for Prefetches and Operands 1 CPU32 Integrated Development Support Development Support 18. In-Circuit Emulator Configuration 20. BDM Block Diagram 19. BDM Source Summary Source BDM Enabled BDM Disabled Atemp 20. Polling the BDM Entry Source Freescale Encoding Data Message Type 21. CPU Generated Message Encoding 22. Debug Serial I/O Block Diagram 23. Serial Interface Timing Diagram 25. Bkpt Timing for Forcing BDM 24. Bkpt Timing for Single Bus Cycle 22. Size Field Encoding BDMEncoding Operand Size 74MC68340 USER’S Manualmotorola 27. Command-Sequence Diagram Command 23. BDM Command Summary WDREG/WAREG System Register Select Code 24. Register Field for Rsreg and Wsreg MS Addr Operand Data Dump Long 82MC68340 USER’S Manualmotorola Write Memory Location XXX Not Ready Next CMD CMD Complete 84MC68340 USER’S Manualmotorola Chkstat MOVE.B SRA,D0 Command Format Command Sequence 28. Functional Model of Instruction Pipeline Deterministic Opcode Tracking 29. Instruction Pipeline Timing Diagram Resource Scheduling Instruction Execution Timing 30. Block Diagram of Independent Resources 31. Simultaneous Instruction Execution 32. Attributed Instruction Times Freescale Semiconductor, Inc Instructions Instruction Stream Timing Examples 33. Example 1-Instruction Stream BRA.W Faraway MOVE.L 35. Example 2-Branch Not Taken Instruction Timing Tables 98MC68340 USER’S Manualmotorola Instruction Head Tail Cycles 100MC68340 USER’S Manualmotorola Head Tail Cycles 102MC68340 USER’S Manualmotorola DIVU.W 104MC68340 USER’S Manualmotorola #, Dn 20/1/0 106MC68340 USER’S Manualmotorola 〈CEA 〉 40/1/x Clocks Shift Counts #, Dn 60/2/0 110MC68340 USER’S Manualmotorola BSR.B BSR.W BSR.L CHK 112MC68340 USER’S Manualmotorola Berr on instruction Section DMA Controller Module DMA Module Overview Single-Address Transfers Transfer Request Generation DMA Module Signal Definitions External Request Generation Data Transfer Modes Single-Address Mode Freescale Semiconductor, Inc Single-Address Read Timing External Burst Single-Address Read Timing Cycle Steal Single-Address Write Timing External Burst Single-Address Write Timing Cycle Steal Freescale Semiconductor, Inc Dual-Address Mode Dual-Address Read Timing External Burst-Source Requesting 10. Dual-Address Read Timing Cycle Steal-Source Requesting MOTOROLAMC68340 USER’S MANUAL6 Inc CPU Cycle DMA Read Channel Initialization and Startup DMA Channel Operation Data Transfers Channel Termination 13. Fast Termination Option Cycle Steal 14. Fast Termination Option External Burst-Source Requesting Register Description 15. DMA Module Programming Model Module Configuration Register MCR FRZx Control Bits MCR1, MCR2Action Freescale Semiconductor, Inc Channel Control Register CCR Interrupt Register IntrINTR1, INTR2 CCR1, CCR2 Bit Definition SSIZEx Encoding REQ Field BB Field Bus Bandwidth Bit Definition DSIZEx EncodingREQx Encoding BBx Encoding and Bus Bandwidth CSR1, CSR2 Channel Status Register CSR Freescale Semiconductor, Inc FCR1, FCR2 Freescale Semiconductor, Inc Function Code Register FCR Destination Address Register DAR Freescale Semiconductor, Inc Source Address Register SARSAR1, SAR2 DAR1, DAR2 Byte Transfer Counter Register BTCBTC1, BTC2 16. Packing and Unpacking of Operands Data Packing DMA Channel Initialization Sequence DMA Channel Configuration Freescale Semiconductor, Inc DMACH1 EQU DMA Channel Example Configuration CodeDMAMCR1 EQU DMAFCR1 EQU DMAINT1 EQUDMACCR1 EQU DMACSR1 EQU LEA Daradd EQU MOVE.L DARADD,DMADAR1A0 MOVE.B #$DD,DMAFCR1A0MOVE.W #$0E8D,DMACCR1A0 END MOVE.W Modbase EQU MOVE.W #$068D,DMACCR1A0 END $6001 Source address is an ODD address MOVE.W #$1DB1,DMACCR1A0 END Section Serial Module Local Loopback -Remote Loopback Internal Channel Control Logic Baud Rate Generator LogicInterrupt Control Logic Comparison of Serial Module to MC68681 Serial Module Signal Definitions Crystal Output Crystal Input or External Clock Channel B Transmitter Serial Data Output TxDB Freescale Semiconductor, Inc External Input SclkChannel a Transmitter Serial Data Output TxDA Channel a Receiver Serial Data Input RxDA Channel a Receiver Ready R≈RDYA Channel a Clear-To-Send CtsaChannel B Clear-To-Send Ctsb Channel a Transmitter Ready T≈RDYA Baud Rate Generator OperationTransmitter and Receiver Operating Modes Transmitter and Receiver Functional Diagram Transmitter Timing Diagram MOTOROLAMC68340 USER’S MANUAL7 Receiver Timing Diagram Freescale Semiconductor, Inc Freescale Semiconductor, Inc Looping Modes Looping Modes Functional Diagram Multidrop Mode Multidrop Mode Timing Diagram Register Description Register Description and Programming 18MC68340 USER’S Manualmotorola Serial Module Programming Model Freeze ILR MR1A, MR1B IVR PMx and PT Control Bits Parity Mode Parity Type SRA, SRB B/Cx Control Bits Freescale Semiconductor, Inc RCSx Control Bits CSRA, CsrbSet CRA, CRB TCSx Control Bits MISC3 MISC2 MISC1 MISC0 MISCx Control Bits TCx Control Bits RBA, RBB RCx Control Bits Ipcr TBA, TBB ISR ACR Freescale Semiconductor, Inc IER $71D Opcr Bit Set Bit Reset CMx Control Bits MR2A, MR2B Length 6-8 Bits Length 5 Bits 10. SBx Control Bits Freescale Semiconductor, Inc Programming 10. Serial Module Programming Flowchart 1 10. Serial Module Programming Flowchart 2 10. Serial Module Programming Flowchart 3 10. Serial Module Programming Flowchart 4 10. Serial Module Programming Flowchart 5 Serial Module Initialization Sequence Serial Module Configuration Mcrl EQU Serial Module Example Configuration CodeSerial EQU Mcrh EQU Mode Register MOVE.B Wait for Transmitter Empty or Timeout MOVE.WNegate Rtsa Signal Output MOVE.B Reset RECEIVER/TRANSMITTER MOVE.B MOVE.B #$BB,CSRAA0 Mode RegisterSET UP Baud Rate for Port in Clock Select Register Enable Port Section Timer Modules Timer and Counter Functions Internal Control Logic Timer Functional Diagram Freescale Semiconductor, Inc Interrupt Control Logic Timer Modules Signal Definitions Timer Input TIN1, TIN2 Input Capture/Output Compare Timer Gate TGATE1, TGATE2Timer Output TOUT1, TOUT2 Operating Modes TGATE≈ Square-Wave Generator Square-Wave Generator Mode Variable Duty-Cycle Square-Wave Generator Variable-Width Single-Shot Pulse Generator Variable Duty-Cycle Square-Wave Generator Mode Variable-Width Single-Shot Pulse Generator Mode Pulse-Width Measurement Pulse-Width Measurement Mode Period Measurement Event Count Period Measurement Mode 10. Event Count Mode Freescale Semiconductor, Inc Timer Bypass OC1 OC0 TOUTx OCx Encoding 11. Timer Module Programming Model FRZ1 FRZ0 Action Control Register CR Freescale Semiconductor, Inc Interrupt Register IR IEx Encoding Enabled Interrupts Division TOUTx ModePOT Encoding MODEx Encoding Status Register SR 24MC68340 USER’S Manualmotorola Preload 1 Register PREL1 Counter Register CntrCntr PREL2 Preload 2 Register PREL2Compare Register COM PREL1 Timer Module Configuration Timer Module Initialization Sequence Timer Module Example Configuration Code CLR.W COM1A0 BEQ.B LOOP2 BNE.B LOOP1 MOVE.W CNTR1A0,D0 NOT.W D0 ADDQ.W #$1,DO BEQ.B LOOP3 Non-IEEE 1149.1 Operation for details Section Ieee 1149.1 Test Access Port TAP Controller Test Access Port Block Diagram TAP Controller State Machine Boundary Scan Register Name Bit Number Boundary Scan Control Bits Type CTL Cell Num Cell Type Boundary Scan Bit DefinitionsPin/Cell Output Pin/Cell Output Num Cell Type Ipipe Pin/Cell Output Bit Num Cell Type Freescale Semiconductor Active-High Output Control Cell IO.Ctl1 Bidirectional Data Cell IO.Cell Instruction Register SAMPLE/PRELOAD ExtestCode Instruction HI-Z Bypass X1XMC68340 Restrictions NON-IEEE 1149.1 Operation Processor Clock Circuitry Minimum System Configuration Sample Crystal Circuit Sram Interface Reset Circuitry Serial Interface ROM Interface Memory Interface Information Using an 8-Bit Boot ROM Bit Boot ROM Timing Access Time Calculations Memory Access Times at 16.78 MHz Calculating Frequency-Adjusted OutputAccess Time 12. Signal Width Specifications 13. Skew between Two Outputs CD-I, CD-ROM Power Consumption Considerations 15. MC68340 Current vs. Activity at 5 16. MC68340 Current vs. Voltage/Temperature Advantage Benefit Typical Electrical CharacteristicsFreescale Semiconductor, Inc 10.3.2 MC68340V 3.3 Parameter Maximum Ratings Thermal CharacteristicsRating Symbol Value Unit Characteristic Symbol Value Unit PI/O Power ConsiderationsAC Electrical Specification Definitions Pint + PI/O MOTOROLAMC68340 USER’S MANUAL11-3 Drive Levels and Test Points for AC Specifications CLKOUT, FREEZE, IPIPE, Ifetch Characteristic Symbol Min Max Unit 11-6MC68340 USER’S Manualmotorola MOTOROLAMC68340 USER’S MANUAL11-7 39 MHz 16.78 MHz 25.16 MHz Symbol Min Max Unit Num.Characteristic 25.16 MHz Num Characteristic Symbol Min Max Unit Freescale Semiconductor, Inc AC Timing Specifications 39 MHz 16.78 MHz Num Characteristic Symbol Min Max Read Cycle Timing Diagram Write Cycle Timing Diagram Fast Termination Read Cycle Timing Diagram Fast Termination Write Cycle Timing Diagram Bus Arbitation Timing-Active Bus Case Bus Arbitration Timing-Idle Bus Case Iack Cycle Timing Diagram 10. Background Debug Mode Serial Port Timing Or 5.0 39 MHz 25.16 MHz Num Characteristic Min Max Min Max Unit 13. Timer Module Clock Signal Timing Diagram Freescale 15. Serial Module General Timing Diagram 16. Serial Module Asynchronous Mode Timing 19. Test Clock Input Timing Diagram 20. Boundary Scan Timing Diagram Standard MC68340 Ordering Information Section Ordering Information and Mechanical Data 12-2MC68340 USER’S Manualmotorola VCC GND Pin Group FE Suffix 12-4MC68340 USER’S Manualmotorola Pin Group RP Suffix 12-6 DIM MIN MAX Freescale Semiconductor, Inc RP Suffix D E CTS Dsack Index-4 USER’S Manual Freescale Semiconductor, Inc Motorola MC68340 USER’S Manual Index-8 Index-9