Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE≈ is enabled (TGE bit in the CR is set), then asserting TGATE≈. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL1 register (N1). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first timeout can range from N1 to N1 + 1 periods. When TGATE≈ is used to enable the counter, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see Section 11 Electrical Characteristics.

If the counter counts down to the value stored in the COM, the COM and TC bits in the SR are set. The counter continues counting down to timeout. At this time, the SR TO bit is set and the SR COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. After the second timeout, the selected clock is held high, disabling the prescaler and counter. Additionally, the SR ON and COM bits are cleared.

TOUTx behaves as a variable-width pulse when the OCx bits of the CR are programmed for toggle mode. TOUTx is a logic zero between the time that the timer is enabled and the first timeout. When this event occurs, TOUTx transitions to a logic one. The second timeout occurs after N2 + 1 periods (allowing for the zero cycle), resulting in TOUTx returning to a logic zero (see Figure 8-7). The OUT bit in the SR reflects the level of TOUTx.

COUNTER

 

 

 

 

 

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

COUNTER

0

0

2

1

0

5

4

3

2

1

0

TOUT

 

 

N1: N1 + 1

 

 

 

 

N2 + 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENABLE

 

 

TIMEOUT

 

 

 

 

 

TIMEOUT

MODEx Bits in Control Register = 011

Preload 1 Register = N1 = 2

Preload 2 Register = N2 = 5

OCx bits in Control Register = 01

Figure 8-7. Variable-Width Single-Shot Pulse Generator Mode

If TGATE≈ is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE≈ was negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE≈ is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE≈ was negated. The ON bit is set again.

If TGATE≈ is not enabled (TGE = 0), TGATE≈ has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock

MOTOROLAMC68340 USER’S MANUAL8- 11

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Motorola MC68340 manual Variable-Width Single-Shot Pulse Generator Mode
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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