Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

to its location in the SR. See Figure 8-4 for a depiction of this mode. If the timing gate is disabled (CR TGE bit is cleared), TGATE≈ has no effect on the operation of the timer; thus the input capture function is inoperative. At all times, the TGATE≈ level bit (TGL) in the SR reflects the level of the TGATE≈ signal.

COUNTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COUNTER

0

0

0

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

0

0

8

8

7

7

COUNTER

0

0

0

0

8

8

7

7

6

6

6

6

6

6

6

3

2

2

1

1

0

0

8

8

8

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TGATE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TG SET

 

 

 

TG CLEARED

 

 

 

 

 

 

TG SET

 

TOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENABLE

 

TC SET

 

 

 

 

 

 

 

 

 

 

 

 

TIMEOUT

 

 

TC SET

 

Modex Bits in Control Register = 000

Preload 1 Register = 8

Compare Register = 7

TGE Bit of Status Register = 1

TG Bit in Status Register Initially = 0

OCx Bits in Control Register = 10

Figure 8-4. Input Capture/Output Compare Mode

Since the counter is not affected by TGATE≈, it continues to decrement on the falling edge of the counter clock and load from the PREL1 at timeout, regardless of the value of

TGATE≈.

When the counter counts down to the value contained in the COM, this condition is reflected by setting the timer compare (TC) and compare (COM) bits in the SR. TOUTx responds as selected by the OCx bits in the CR. The output level (OUT) bit in the SR reflects the value on TOUTx. Shadowing does not affect this operation.

If the counter counts down to $0000, a timeout is detected, causing the SR timeout interrupt (TO) bit to be set and the SR COM bit to be cleared. On the next falling edge of the counter clock after the timeout is detected, the value in PREL1 is again loaded into the counter. TOUTx responds as selected by the CR OCx bits.

A square-wave generator can be implemented by programming the CR OCx bits to toggle mode. The value in the COM should be one-half the value in PREL1 to cause an event to happen twice in the countdown.

This mode can be used as a pulse-width modulator by programming the CR OCx bits to zero mode or one mode. The value in the PREL1 specifies the frequency, and the COM determines the pulse width. The pulse widths can be changed by writing a new value to the COM.

MOTOROLAMC68340 USER’S MANUAL8- 7

For More Information On This Product,

Go to: www.freescale.com

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Motorola MC68340 manual Tgate≈
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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