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Motorola MC68340 Freescale Semiconductor, Inc Address Bus A31-A0, Bus Cycle Termination Signals

Models: MC68340

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

3.1.3 Address Bus (A31–A0)

These signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted.

3.1.4 Address Strobe (AS)

This output timing signal indicates the validity of many control signals and the address on the address bus. AS is asserted approximately one-half clock cycle after the beginning of a bus cycle.

3.1.5 Data Bus (D15–D0)

This bidirectional, nonmultiplexed, parallel bus contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle. During a read cycle, the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle.

3.1.6 Data Strobe (DS)

DS is an output timing signal that applies to the data bus. For a read cycle, the MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle.

3.1.7 Bus Cycle Termination Signals

The following signals can terminate a bus cycle.

3.1.7.1DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS (DSACK1 AND DSACK0). During bus cycles, external devices assert DSACK1 and/or DSACK0 as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the MC68340 the size of the port for the bus cycle just completed (see Table 3-3). Refer to 3.3.1 Read Cycle for timing relationships of DSACK1 and DSACK0.

Additionally, the system integration module (SIM40) chip select address mask register can be programmed to internally generate DSACK1 and DSACK0 for external accesses, eliminating logic required to generate these signals. However, if external DSACK≈ signals are returned earlier than indicated by the DD bits in the chip select address mask register, the cycle will terminate sooner than programmed. Refer to Section 4 System Integration Module for additional information. The SIM40 can alternatively be programmed to generate a fast termination cycle, providing a two-cycle external access. Refer to 3.2.6 Fast Termination Cycles for additional information on these cycles.

3- 4MC68340 USER’S MANUALMOTOROLA

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Motorola MC68340 manual Freescale Semiconductor, Inc Address Bus A31-A0, Bus Cycle Termination Signals
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.