Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

3.1.7.2BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACK≈ to indicate a bus error condition. BERR can also be asserted in conjunction with DSACK≈ to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 11 Electrical Characteristics. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 3.5 Bus Exception Control Cycles for additional information on the use of these signals.

The internal bus monitor can be used to generate an internal bus error signal for internal and internal-to-external transfers. If the bus cycles of an external bus master are to be monitored, external BERR generation must be provided since the internal bus error monitor has no information about transfers initiated by an external bus master.

3.1.7.3AUTOVECTOR (AVEC).This signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68340 should internally generate a vector (autovector) number to locate an interrupt handler routine. AVEC can be generated either externally or internally by the SIM40 (see Section 4 System Integration Module for additional information). AVEC is ignored during all other bus cycles.

3.2 DATA TRANSFER MECHANISM

The MC68340 supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACK0. The MC68340 also supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of synchronous cycles controlled by the fast termination capability of the SIM40.

3.2.1 Dynamic Bus Sizing

The MC68340 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68340 through the use of the DSACK≈ inputs. Refer to Table 3-3 for DSACK≈ encoding.

Table 3-3. DSACK≈ Encoding

DSACK1

DSACK0

Result

1

1

 

(Negated)

(Negated)

Insert Wait States in Current Bus Cycle

1

0

 

(Negated)

(Asserted)

Complete Cycle—Data Bus Port Size Is 8 Bits

0

1

 

(Asserted)

(Negated)

Complete Cycle—Data Bus Port Size Is 16 Bits

0

0

Reserved—Defaults to 16-Bit Port Size Can Be

(Asserted)

(Asserted)

Used for 32-Bit DMA cycles

MOTOROLAMC68340 USER’S MANUAL3- 5

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Motorola MC68340 manual Data Transfer Mechanism, Dynamic Bus Sizing
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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