DMA Channel Initialization Sequence | Motorola MC68340 instruction

Freescale Semiconductor, Inc.

For normal transfers aligned with the size and address, only two bus cycles are required for each transfer: a read from the source and a write to the destination.

6.9 DMA CHANNEL INITIALIZATION SEQUENCE

The following paragraphs describe DMA channel initialization and operation. If the DMA capability of the MC68340 is being used, the initialization steps should be performed during the part initialization sequence. The mode operation steps should be performed to start a DMA transfer. The DONE≈ pin requires an external pullup resistor even if operating only in the internal request mode.

6.9.1 DMA Channel Configuration

The following steps can be accomplished in any order when initializing the DMA channel. These steps need to be performed for each channel used.

Module Configuration Register (MCR)

•Clear the stop bit (STP) for normal operation. (Only one STP bit exists for both channels.)

•Select whether to respond to or ignore FREEZE (FRZx bits). (Only one set of FRZx bits exits for both channels.)

•If desired, enable the external data bus operation in single-address mode (SE bit).

•Program the interrupt service mask to set the level below which interrupts are ignored during a DMA transfer (ISM bits). The channel will begin operation when the level of the CPU32 SR I2-I0 bits is less than or equal to the level of the DMA ISM bits.

•Select the access privilege for the supervisor/user registers (SUPV bit).

•Program the master arbitration ID (MAID) to establish priority on the IMB between both DMA channels. Note that the two DMA channels should have distinct MAIDs if both channels are being used. (If they are programmed the same, channel 1 has priority.)

•Select the interrupt arbitration level for the DMA channel (IARB bits). (Only one set of IARB bits exits for both channels.)

Interrupt Register (INTR)

•Program the interrupt priority level for the channel interrupt (INTL bits).

•Program the vector number for the channel interrupt (INTV bits).

Channel Control Register (CCR)

•If desired, enable the interrupt when breakpoint is recognized and the channel is the bus master (INTB bit).

•If desired, enable the interrupt when done without an error condition (INTN bit).

•If desired, enable the interrupt when the channel encounters an error (INTE bit).

6- 36MC68340 USER’S MANUALMOTOROLA

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola MC68340 manual DMA Channel Initialization Sequence, DMA Channel Configuration

Models: MC68340

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

6.9 DMA CHANNEL INITIALIZATION SEQUENCE

6.9.1 DMA Channel Configuration

MC68340 specifications