Motorola MC68340 manual DSACK≈, BERR, and Halt Assertion Results, Asserted on Rising Edge of State

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

EXAMPLE B: A system uses error detection and correction on RAM contents. The designer may:

1.Delay DSACK≈ until data is verified and assert BERR and HALT simultaneously to

indicate to the MC68340 to automatically retry the error cycle (case 5), or if data is valid, assert DSACK≈ (case 1).

2.Delay DSACK≈ until data is verified and assert BERR with or without DSACK≈ if data is in error (case 3). This initiates exception processing for software handling of the condition.

3.Return DSACK≈ prior to data verification; if data is invalid, BERR is asserted on the next clock cycle (case 4). This initiates exception processing for software handling of the condition.

4.Return DSACK≈ prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry.

Table 3-4. DSACK≈, BERR, and HALT Assertion Results

Asserted on Rising

Edge of State

Case	Control
Num	Signal	N	N + 2	Result
1	DSACK≈	A	S	Normal cycle terminate and continue.
	BERR	NA	NA
	HALT	NA	X
2	DSACK≈	A	S	Normal cycle terminate and halt; continue
	BERR	NA	NA	when HALT negated.
	HALT	A/S	S
3	DSACK≈	NA/A	X	Terminate and take bus error exception,
	BERR	A	S	possibly deferred.
	HALT	NA	X
4	DSACK≈	A	X	Terminate and take bus error exception,
	BERR	NA	A	possibly deferred.
	HALT	NA	NA
5	DSACK≈	NA/A	X	Terminate and retry when HALT negated.
	BERR	A	S
	HALT	A/S	S
6	DSACK≈	A	X	Terminate and retry when HALT negated.
	BERR	NA	A
	HALT	NA	A

NOTES:

N— Number of the current even bus state (e.g., S2, S4, etc.) A — Signal is asserted in this bus state

NA — Signal is not asserted in this state

X — Don't care

S — Signal was asserted in previous state and remains asserted in this state

MOTOROLAMC68340 USER’S MANUAL3- 33

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