14MC68340 USER’S Manualmotorola | Motorola instruction

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4.2.4.1PROGRAMMABLE FEATURES. The chip select function supports the following programmable features:

Four Programmable Chip Select Circuits

All four chip select circuits are independently programmable from the same list of selectable features. Each chip select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select. The base address register selects the starting address for the address block in 256-byte increments. The address mask register specifies the size of the address block range. The base address register V-bit indicates that the register information for that chip select is valid. A global chip select (CS0) allows address decode for a boot ROM before system initialization occurs.

Variable Block Sizes

The block size, starting from the specified base address, can vary in size from 256 bytes up to 4 Gbytes in 2n increments. The specified base address must be on a multiple of the the block size. The block size is specified in the address mask register.

Both 8- and 16-Bit Ports Supported

The 8-bit ports are accessible on both odd and even addresses when connected to data bus bits 15–8; the 16-bit ports can be accessed as odd bytes, even bytes, or even words. The port size is specified by the PS bits in the address mask register.

Write Protect Capability

The WP bit in each base address register can restrict write access to its range of addresses.

Fast Termination Option

Programming the FTE bit in the base address register for the fast termination option causes the chip select to terminate the cycle by asserting the internal DSACK≈ early, providing a two-cycle external access.

Internal DSACK≈ Generation for External Accesses with Programmable Wait States

DSACK≈ can be generated internally with up to three wait states for a particular device using the DD bits in the address mask register.

Full 32-Bit Address Decode with Address Space Checking

The FC bits in the base address register and FCM bits in the address mask register are used to select address spaces for which the chip selects will be asserted.

4.2.4.2GLOBAL CHIP SELECT OPERATION. Global chip select operation allows address decode for a boot ROM before system initialization occurs. CS0 is the global chip select output, and its operation differs from the other external chip select outputs following reset. When the CPU32 begins fetching after reset, CS0 is asserted for every address until the V-bit is set in the CS0 base address register.

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola manual 14MC68340 USER’S Manualmotorola

Models: MC68340

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

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MC68340 specifications