Motorola manual 30MC68340 USER’S Manualmotorola

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

data will be ignored if AVEC is asserted before or at the same time as the DSACK≈ signals. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of DSACK≈ during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number (the sum of the interrupt level plus 24 ($18)).

AVEC is multiplexed with CS0. The FIRQ bit in the SIM40 module configuration register controls whether the AVEC/CS0 pin is used as an autovector input or as CS0 (refer to Section 4 System Integration Module for additional information). AVEC is only sampled during an interrupt acknowledge cycle. During all other cycles, AVEC is ignored. Additionally, AVEC can be internally generated for external devices by programming the autovector register. Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7–IRQ1. Figure 3-16 shows the timing for an autovector operation.

3.4.4.3SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or external, are arbitrated internally. When no internal module (including the SIM40, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition. The MC68340 automatically generates the spurious interrupt vector number (24) instead of the interrupt

vector number in this case. When an external device does not respond to an interrupt acknowledge cycle with AVEC or DSACK≈, a bus monitor must assert BERR, which results in the CPU32 taking the spurious interrupt vector. If HALT is also asserted, the MC68340 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector.

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