Motorola manual 98MC68340 USER’S Manualmotorola

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

four. If there is no time in the head to perform a prefetch due to a previous trailing write, then additional time to perform the prefetches must be allotted in the middle of the instruction or after the tail.

8 (2 /1 /0)

TOTAL NUMBER OF CLOCKS

NUMBER OF READ CYCLES

NUMBER OF INSTRUCTION ACCESS CYCLES

NUMBER OF WRITE CYCLES

The total number of clocks for bus activity is as follows:

(2 Reads ⋅ 2 Clocks/Read) + (1 Instruction Access ⋅ 2 Clocks/Access) +

(0 Writes ⋅ 2 Clocks/Write) = 6 Clocks of Bus Activity

The number of internal clocks (not overlapped by bus activity) is as follows:

10 Clocks Total − 6 Clocks Bus Activity = 4 Internal Clocks

Memory read requires two bus cycles at two clocks each. This read time, implied in the tail figure for the EA, cannot be overlapped with the instruction because the instruction has a head of zero. An additional two clocks are required for the ADD instruction itself. The total is 6 + 4 + 2 = 12 clocks. If bus cycles take more time (i.e., the memory is off-chip), add an appropriate number of clocks to each memory access.

The instruction sequence MOVE.L D0, (A0) followed by LSL.L #7, D2 provides an example of overlapped execution. The MOVE instruction has a head of zero and a tail of four because it is a long write. The LSL instruction has a head of four. The trailing write from the MOVE overlaps the LSL head completely. Thus, the two-instruction sequence has a head of zero and a tail of zero, and a total execution of 8 rather than 12 clocks.

General observations regarding calculation of execution time are as follows:

•Any time the number of bus cycles is listed as "X", substitute a value of one for byte and word cycles and a value of two for long cycles. For long bus cycles, usually add a value of two to the tail.

•The time calculated for an instruction on a three-clock (or longer) bus is usually longer than the actual execution time. All times shown are for two-clock bus cycles.

•If the previous instruction has a negative tail, then a prefetch for the current instruction can begin during the execution of that previous instruction.

•Certain instructions requiring an immediate extension word (immediate word EA, absolute word EA, address register indirect with displacement EA, conditional branches with word offsets, bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DBcc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements.

5- 98MC68340 USER’S MANUALMOTOROLA

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