Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

for at least one system clock period plus the sum of the setup and hold times for TINx. Refer to Section 11 Electrical Characteristics, for additional information.

8.2.2Timer Gate (TGATE1, TGATE2)

This active-low input can be programmed to enable and disable the counter and prescaler. TGATE≈ may also be programmed to be a simple input. For more information on the modes of operation, refer to 8.3 OPERATING MODES. To guarantee that the timer recognizes a valid level on TGATE≈, the signal is synchronized with the system clock. Additionally, the high and low levels of this input must each be stable for at least one system clock period plus the sum of the setup and hold times for TGATE≈. Refer to Section 11 Electrical Characteristics , for additional information.

8.2.3 Timer Output (TOUT1, TOUT2)

This output drives the various output waveforms generated by the timer. The initial level and transitions can be programmed by the output control (OC) bits in the CR.

8.3 OPERATING MODES

The following paragraphs contain a detailed description of each timer operation mode and of the IMB operation during accesses to the timer. Changing the contents of the CR should only be attempted when the timer is disabled (the software reset (SWR) bit in the CR is cleared). Changing the CR while the timer is running may produce unpredictable results.

8.3.1 Input Capture/Output Compare

This mode has the capability of capturing a counter value by holding the value in the counter register (CNTR). Additionally, this mode can provide compare information via TOUTx to indicate when the counter has reached the compare value. This mode can be used for square-wave generation, pulse-width modulation, or periodic interrupt generation. This mode can be selected by programming the operation mode bits (MODEx) in the CR to 000.

The timer is enabled when the counter prescaler enable (CPE) and SWRx bits in the CR are set. Once enabled, the counter enable (ON) bit in the SR is set, and the next falling edge of the counter clock causes the counter to be loaded with the value in the preload 1 register (PREL1).

The TGATE≈ signal functions differently in this mode than it does in the other modes. TGATE≈ does not enable or disable the counter/prescaler input clock; instead, it is used to disable shadowing. Normally, the counter is decremented on the falling edge of the counter clock, and the CNTR is updated on the next rising edge of the system clock; thus, the CNTR shadows the actual value of the counter. The timer gate interrupt (TG) bit in the SR must be cleared for shadowing to occur. TGATE≈ is used to set the TG bit and disable shadowing. If the timing gate is enabled (TGE bit of the CR is set), the TG bit is set by the rising edge of TGATE≈. Shadowing is disabled until the TG bit is cleared by writing a one

8- 6MC68340 USER’S MANUALMOTOROLA

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Motorola MC68340 manual Timer Gate TGATE1, TGATE2, Timer Output TOUT1, TOUT2, Operating Modes, Input Capture/Output Compare
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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