Deriving Software Watchdog Timeout, MHz External

Freescale Semiconductor, Inc.

SWT1, SWT0—Software Watchdog Timing

These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula:

divide count

EXTAL frequency

The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator.

Table 4-7. Deriving Software Watchdog Timeout

					32.768-kHz	16.777-MHz External
SWP	SWT1	SWT0	Software Timeout Period		Crystal Period	Clock Period
0	0	0	29/EXTAL Input Frequency		15.6 ms	30 ∝s
0	0	1	211	/EXTAL Input Frequency	62.5 ms	122 ∝s
0	1	0	213	/EXTAL Input Frequency	250 ms	488 ∝s
0	1	1	215	/EXTAL Input Frequency	1 s	1.95 ms
1	0	0	218	/EXTAL Input Frequency	8 s	15.6 ms
1	0	1	220	/EXTAL Input Frequency	32 s	62.5 ms
1	1	0	222 /EXTAL Input Frequency		128 s	250 ms
1	1	1	224	/EXTAL Input Frequency	512 s	1 s

NOTE: When the SWP and SWT bits are modified to select a software timeout other than the default, the software service sequence ($55 followed by $AA written to the software service register) must be performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for more information.

DBFE—Double Bus Fault Monitor Enable

1 = Enable double bus fault monitor function.

0 = Disable double bus fault monitor function.

For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32.

BME—Bus Monitor External Enable

1 = Enable bus monitor function for an internal-to-external bus cycle. 0 = Disable bus monitor function for an internal-to-external bus cycle.

For more information see 4.2.2.2 Internal Bus Monitor .

BMT1, BMT0—Bus Monitor Timing

These bits select the timeout period for the bus monitor (see Table 4-8). Upon reset, the bus monitor is set to 64 system clocks.

MOTOROLAMC68340 USER’S MANUAL4- 25

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola MC68340 manual Deriving Software Watchdog Timeout, MHz External

Models: MC68340

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Table 4-7. Deriving Software Watchdog Timeout

16.777-MHz External

Software Timeout Period

Crystal Period

Clock Period

For more information see 4.2.2.2 Internal Bus Monitor .

MC68340 specifications