Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

Table 5-11. System Control Operations

 

Operand

 

 

Instruction

Syntax

Operand Size

Operation

 

 

Privileged

ANDI

#〈data〉, SR

16

Immediate Data Λ SR ⇒ SR

EORI

#〈data〉, SR

16

Immediate Data ⊕ SR ⇒ SR

MOVE

〈ea〉, SR

16

Source ⇒ SR

 

SR, 〈ea〉

16

SR ⇒ Destination

MOVEA

USP, An

32

USP ⇒ An

 

An, USP

32

An ⇒ USP

MOVEC

Rc, Rn

32

Rc ⇒ Rn

 

Rn, Rc

32

Rn ⇒ Rc

MOVES

Rn, 〈ea〉

8, 16, 32

Rn ⇒ Destination using DFC

 

〈ea〉, Rn

 

Source using SFC ⇒ Rn

ORI

#〈data〉, SR

16

Immediate Data V SR ⇒ SR

RESET

none

none

Assert RESET line

RTE

none

none

(SP) ⇒ SR; SP + 2 ⇒ SP; (SP) ⇒ PC; SP + 4 ⇒

 

 

 

SP; restore stack according to format

STOP

#〈data〉

16

Immediate Data ⇒ SR; STOP

LPSTOP

#〈data〉

none

Immediate Data ⇒ SR; interrupt mask ⇒ EBI;

 

 

 

STOP

 

 

Trap Generating

BKPT

#〈data〉

none

If breakpoint cycle acknowledged, then execute

 

 

 

returned operation word, else trap as illegal

 

 

 

instruction.

BGND

none

none

If background mode enabled, then enter background

 

 

 

mode, else format/vector offset ⇒ – (SSP);

 

 

 

PC ⇒ – (SSP); SR ⇒ – (SSP); (vector) ⇒ PC

CHK

〈ea〉, Dn

16, 32

If Dn < 0 or Dn < (ea), then CHK exception

CHK2

〈ea〉, Rn

8, 16, 32

If Rn < lower bound or Rn > upper bound, then

 

 

 

CHK exception

ILLEGAL

none

none

SSP – 2 ⇒ SSP; vector offset ⇒ (SSP);

 

 

 

SSP – 4 ⇒ SSP; PC ⇒ (SSP);

 

 

 

SSP – 2 ⇒ SSP; SR ⇒ (SSP);

 

 

 

llegal instruction vector address ⇒ PC

TRAP

#〈data〉

none

SSP – 2 ⇒ SSP; format/vector offset ⇒ (SSP);

 

 

 

SSP – 4 ⇒ SSP; PC ⇒ (SSP); SR ⇒ (SSP);

 

 

 

vector address ⇒ PC

TRAPcc

none

none

If cc true, then TRAP exception

 

#〈data〉

16, 32

 

TRAPV

none

none

If V set, then overflow TRAP exception

 

 

Condition Code Register

ANDI

#〈data〉, CCR

8

Immediate Data Λ CCR ⇒ CCR

EORI

#〈data〉, CCR

8

Immediate Data ⊕ CCR ⇒ CCR

MOVE

〈ea〉, CCR

16

Source ⇒ CCR

 

CCR, 〈 ea〉

16

CCR ⇒ Destination

ORI

#〈data〉, CCR

8

Immediate Data V CCR ⇒ CCR

5- 28MC68340 USER’S MANUALMOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Page 164 Page 166
Page 165
Image 165
Motorola MC68340 manual System Control Operations, Privileged, Trap Generating, Condition Code Register
Page 164 Page 166

MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
Top Page Image Contents