Motorola MC68340 manual Example 2-Branch Not Taken, BRA.W Faraway MOVE.L

Freescale Semiconductor, Inc.

1 2 3 4 5 6 7 8 9 0 1 2 3 4

CLOCK

BUS CONTROLLER

INSTRUCTION CONTROLLER

EXECUTION TIME

1 PRE-	2 PRE-		3 PRE-	4 PRE-		WRITE	WRITE
FETCH	FETCH		FETCH	FETCH		FOR 4	FOR 4
MOVEQ	CMP	OFFSET	NOT	MOVE TO
		CALC	TAKEN	(A0)
MOVEQ
	CMP	BLE.B NOT TAKEN			MOVE.L D1,(AO)
#7,D1	D1,D0

Freescale Semiconductor, Inc.

Figure 5-35. Example 2—Branch Not Taken

5.7.2.3TIMING EXAMPLE 3—NEGATIVE TAILS. This example (see Figure 5-36) shows how to use negative tail figures for branches and other change-of-flow instructions. In this example, bus speed is assumed to be four clocks per access. Instruction three is at the branch destination.

Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus; on a slower bus, there is no extra time for the third word.

Instructions

MOVEQ

#7, D1

BRA.W

FARAWAY

MOVE.L

D1, D0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

CLOCK

BUS

BRANCH OFFSET

FETCH MOVE.L

FETCH NEXT

PREFETCH

CONTROLLER

INSTRUCTION

INSTRUCTION

MOVEQ

OFFSET

TAKEN

TAKEN

MOVE

CONTROLLER

CALC

TO D0

EXECUTION

MOVEQ #7,D1

BRA.W FARAWAY

MOVE.L D1,D0

TIME

Figure 5-36. Example 3—Branch Negative Tail

5- 96MC68340 USER’S MANUALMOTOROLA

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