Freescale Semiconductor, Inc.

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CLOCK

BUS CONTROLLER

INSTRUCTION CONTROLLER

EXECUTION TIME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 PRE-

 

2 PRE-

 

3 PRE-

 

4 PRE-

 

 

WRITE

 

 

WRITE

 

FETCH

 

FETCH

 

FETCH

 

FETCH

 

 

FOR 4

 

 

FOR 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOVEQ

 

CMP

OFFSET

NOT

 

MOVE TO

 

 

 

 

 

 

 

 

CALC

TAKEN

 

(A0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOVEQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CMP

BLE.B NOT TAKEN

 

 

MOVE.L D1,(AO)

 

 

#7,D1

 

D1,D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Freescale Semiconductor, Inc.

Figure 5-35. Example 2—Branch Not Taken

5.7.2.3TIMING EXAMPLE 3—NEGATIVE TAILS. This example (see Figure 5-36) shows how to use negative tail figures for branches and other change-of-flow instructions. In this example, bus speed is assumed to be four clocks per access. Instruction three is at the branch destination.

Although the CPU32 has a two-word instruction pipeline, internal delay causes minimum branch instruction time to be three bus cycles. The negative tail is a reminder that an extra two clocks are available for prefetching a third word on a fast bus; on a slower bus, there is no extra time for the third word.

 

 

 

 

 

 

 

 

Instructions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOVEQ

 

 

 

 

#7, D1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BRA.W

 

 

 

 

FARAWAY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOVE.L

 

 

 

 

D1, D0

 

 

 

 

 

 

 

 

 

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CLOCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUS

 

BRANCH OFFSET

 

 

 

 

 

 

FETCH MOVE.L

 

 

 

FETCH NEXT

 

 

 

PREFETCH

CONTROLLER

 

 

 

 

 

 

 

 

 

 

INSTRUCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INSTRUCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOVEQ

 

 

 

OFFSET

 

 

TAKEN

 

 

 

 

 

 

 

 

TAKEN

 

 

 

 

MOVE

CONTROLLER

 

 

 

 

 

CALC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TO D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXECUTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MOVEQ #7,D1

 

 

 

 

 

 

BRA.W FARAWAY

 

 

 

 

 

 

 

 

MOVE.L D1,D0

TIME

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5-36. Example 3—Branch Negative Tail

5- 96MC68340 USER’S MANUALMOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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Motorola MC68340 manual Example 2-Branch Not Taken, BRA.W Faraway MOVE.L
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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