Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
analyzed. To derive the actual instruction execution times for an instruction sequence, the instruction times listed in the tables must be adjusted to account for overlap.
The formula for this calculation is as follows:
C1 − min (T1, H2) + C2 − min (T2, H3) + C3 − min (T3, H4) + .. .. .
where:
CN is the number of cycles listed for instruction N
TN is the tail time for instruction N
HN is the head time for instruction N
min (TN, HM) is the minimum of parameters TN and HM
The number of cycles for the instruction (CN) can include one or two EA calculations in addition to the raw number in the cycles column. In these cases, calculate overall instruction time as if it were for multiple instructions, using the following equation:
〈CEA〉 − min (TEA, HOP) + COP
where:
〈CEA〉 is the instruction’s EA time
COP is the instruction’s operation time
TEA is the EA’s tail time
HOP is the instruction operation’s head time
min (TN, HM) is the minimum of parameters TN and HM
The overall head for the instruction is the head for the EA, and the overall tail for the instruction is the tail for the operation. Therefore, the actual equation for execution time becomes:
COP1 − min (TOP1 , HEA2 ) + 〈CEA〉2 − min (TEA2 , HOP2 ) + COP2 − min (TOP2 , HEA3 ) + . . .
Every instruction must prefetch to replace itself in the instruction pipe. Usually, these prefetches occur during or after an instruction. A prefetch is permitted to begin in the first clock of any indexed EA mode operation.
Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of an instruction provided the bus is not being used. If the bus is being used, then the prefetch occurs at the next available time when the bus would otherwise be idle.
5.7.1.7EFFECTS OF NEGATIVE TAILS. When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a
MOTOROLAMC68340 USER’S MANUAL5- 93
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