Fast Termination Cycles, Fast Termination Timing

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

If a system asserts DSACK≈ for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK≈ (and/or BERR/HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACK≈ (three clocks per cycle). When BERR (or BERR and HALT) is asserted after DSACK≈, BERR (and HALT) must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACK≈ is recognized. This setup time is critical, and the MC68340 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS.

3.2.6 Fast Termination Cycles

With an external device that has a fast access time, the chip select circuit fast termination enable (FTE) can provide a two-clock external bus transfer. Since the chip select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. Refer to Section 4 System Integration Module for more information on chip selects.When fast termination is selected, the DD bits of the corresponding address mask register are overridden. Fast termination can only be used with zero wait states. To use the fast termination option, an external device should be fast enough to have data ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the DSACK≈ timing for a read with two wait states, followed by a fast termination read and write. When using the fast termination option, DS is asserted only in a read cycle, not in a write cycle.

S0	S1	S2 S3 SW SW* SW SW* S4	S5	S0	S1 S4	S5	S0	S1 S4	S5	S0
CLKOUT
AS
DS
R/W
DSACKx
D15–D0
		TWO WAIT STATES IN READ			FAST			FAST
				TERMINATION			TERMINATION
					READ			WRITE

*DSACKx only internally asserted for fast termination cycles.

Figure 3-6. Fast Termination Timing

MOTOROLA

MC68340 USER’S MANUAL

3- 15

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola MC68340 manual Fast Termination Cycles, Fast Termination Timing

Models: MC68340

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

3.2.6 Fast Termination Cycles

TWO WAIT STATES IN READ

Figure 3-6. Fast Termination Timing

MC68340 specifications