MHz 16.78 MHz, Num Characteristic Symbol Min Max

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

11.7 AC TIMING SPECIFICATIONS (Continued)

					3.3 V or
			3.3 V		5.0 V		5.0 V
			8.39 MHz		16.78 MHz		25.16 MHz
Num.	Characteristic	Symbol	Min	Max	Min	Max	Min	Max	Unit
85	DSCLK Cycle	tDSCCYC	2	—	2	—	2	—	CLKOUT
86	CLKOUT High to FREEZE Asserted	tFRZA	0	100	0	50	0	35	ns
87	CLKOUT High to FREEZE Negated	tFRZN	0	100	0	50	0	35	ns
88	CLKOUT High to IFETCH High Impedance	tIFZ	0	100	0	50	0	35	ns
89	CLKOUT High to IFETCH Valid	tIF	0	100	0	50	0	35	ns

NOTES:

(a)The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V ±0.3 V are preliminary and apply only to the appropriate MC68340V low voltage part.

(b)The 16.78-MHz specifications apply to the MC68340 @ 5.0 V ±5% operation.

(c)The 25.16 MHz @ 5.0 V ±5% electrical specifications are preliminary.

(d)For extended temperature parts T A = –40 to +85°C. These specifications are preliminary.

1.All AC timing is shown with respect to 0.8 V and 2.0 V levels unless otherwise noted.

2.This number can be reduced to 5 ns if strobes have equal loads.

3.If multiple chip selects are used, the CS width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select.

4.These hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast termination reads. The user is free to use either hold time for fast termination reads.

5.If the asynchronous setup time (#47) requirements are satisfied, the DSACK≈ low to data setup time (#31) and DSACK≈ low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKOUT low setup time (#27) for the following clock cycle: BERR must only satisfy the late BERR low to CLKOUT low setup time (#27A) for the following clock cycle.

6.To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the current operand transfer are complete and RMC is negated.

7.In the absence of DSACK≈, BERR is an asynchronous input using the asynchronous setup time (#47).

8.Specification #47A for 16.78 MHz @ 3.3 V ±0.3V will be 8 ns.

9.During interrupt acknowledge cycles up to two wait states may be inserted by the processor between states S0 and S1.

11-10MC68340 USER’S MANUALMOTOROLA

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola MC68340 manual MHz 16.78 MHz, Num Characteristic Symbol Min Max

Models: MC68340

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

8.39 MHz

16.78 MHz

Num.

Characteristic

Symbol

Min

Max

MC68340 specifications