MC68340
Freescale Semiconductor, Inc
Freescale Semiconductor, Inc
Preface
CPU32
Table of Contents
Table of Contents
15.4
Section Bus Operation
Section System Integration Module
Section U 3
Pipeline Synchronization with the NOP Instruction
3.1 Types of Faults 3.1.1 Type I-Released Write Faults 3.1.2
2.4 Command Execution 2.5
Section DMA Controller Module
Section Serial Module
Rtsa
OP0
Rtsb
OP1
Section Timer Modules
1.4 Clock Selection Logic
Section Ieee 1149.1 Test Access Port
Section Applications
Table of Contents Concluded
List of Illustrations
List of Illustrations
External and Internal Interface Signals
10-1 Minimum System Configuration Block Diagram 10-2
List of Illustrations Concluded
Xxi
List of Tables
B l e
List of Tables
Section Device Overview
M68300 Family
Advantages
Freescale Semiconductor, Inc Organization
Central Processor Unit
Background Debug Mode
Freescale Semiconductor, Inc 1 CPU32
ON-CHIP Peripherals
System Integration Module
6MC68340 USER’S Manualmotorola
Direct Memory Access Module
Serial Module
Timer Modules
Power Consumption Management
Physical
Compact DISC-INTERACTIVE
More Information
Document Number Document Name
Section Signal Descriptions
Signal Index
Signal Index
Signal Name Mnemonic Function Output
Input
CTSA, Ctsb
Address BUS
Address Bus A23-A0
Address Bus A31-A24
Data BUS D15-D0
Function Codes FC3-FC0
Chip Selects CS3-CS0
Address Space Encoding
Function Code Bits Address Spaces
BUS Control Signals
Interrupt Request Level IRQ7, IRQ6, IRQ5, IRQ3
Data and Size Acknowledge DSACK1, DSACK0
Address Strobe AS
BUS Arbitration Signals
Exception Control Signals
Clock Signals
Instrumentation and Emulation Signals
DMA Module Signals
Serial Module Signals
Timer Signals
Timer Gate TGATE2, TGATE1
Timer Input TIN2, TIN1
Timer Output TOUT2, TOUT1
Test Signals
Synthesizer Power Vccsyn
System Power and Ground VCC and GND
Signal Summary
Signal Summary
Signal Name Mnemonic Input/Output Active State
DACK2, DACK1
BUS Transfer Signals
Section BUS Operation
Bus Control Signals
Input Sample Window
Function Code Signals
SIZx Signal Encoding
Bus Cycle Termination Signals
Freescale Semiconductor, Inc Address Bus A31-A0
Data Transfer Mechanism
Dynamic Bus Sizing
6MC68340 USER’S Manualmotorola
Misaligned Operands
Operand Transfer Cases
OP0 Data BUS
OP0 OP1 Data BUS
Semiconductor
Long-Word Operand Read Timing from 8-Bit Port
Long-Word Operand Write Timing to 8-Bit Port
Long-Word and Word Read and Write Timing-16-Bit Port
Freescale Semiconductor, Inc Bus Operation
Synchronous Operation with DSACK≈
Fast Termination Cycles
Fast Termination Timing
Data Transfer Cycles
Read Cycle
MOTOROLAMC68340 USER’S MANUAL3
Word Write Cycle Flowchart
Freescale Semiconductor, Inc Write Cycle
Read-Modify-Write Cycle
Read-Modify-Write Cycle Timing
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CPU Space Cycles
10. CPU Space Address Encoding
Freescale Semiconductor, Inc Breakpoint Acknowledge Cycle
Freescale Semiconductor, Inc Lpstop Broadcast Cycle
11. Breakpoint Operation Flowchart
12. Breakpoint Acknowledge Cycle Timing Opcode Returned
13. Breakpoint Acknowledge Cycle Timing Exception Signaled
Interrupt Acknowledge Bus Cycles
14. Interrupt Acknowledge Cycle Flowchart
FC3-FC0 CPU Space SIZ0 Byte SIZ1
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16. Autovector Operation Timing
BUS Exception Control Cycles
Signal Result
DSACK≈, BERR, and Halt Assertion Results
Asserted on Rising Edge of State
Control
Freescale Semiconductor, Inc Bus Errors
17. Bus Error without DSACK≈
18. Late Bus Error with DSACK≈
Retry Operation
19. Retry Sequence
Halt Operation
20. Late Retry Sequence
Double Bus Fault
21. Halt Timing
BUS Arbitration
22. Bus Arbitration Flowchart for Single Request
23. Bus Arbitration Timing Diagram-Idle Bus Case
Bus Grant
Freescale Semiconductor, Inc Bus Request
Bus Grant Acknowledge
Freescale Semiconductor, Inc Bus Arbitration Control
Show Cycles
25. Bus Arbitration State Diagram
Reset Operation
26. Show Cycle Timing Diagram
Semiconductor
28. Power-Up Reset Timing Diagram
Section System Integration Module
Module Overview
Module Operation
Module Base Address Register Operation
System Configuration and Protection Operation
SIM40 Module Register Block
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System Configuration and Protection Function
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Software Watchdog Block Diagram
Periodic interrupt timer period Pitr count value
Mode Description
Clock Synthesizer Operation
Clock Operating Modes
Operating
Clock Block Diagram for Crystal Operation
Clock Block Diagram for External Oscillator Operation
Fvco = Fsystem
Clock Control Signals
Chip Select Operation
System Frequencies from 32.768-kHz Reference
= 0 X = = 1 X =
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External Bus Interface Operation
Pin Function Signal PPARA1 = PPARA2 =
Port a Pin Assignment Register
Pin Function Signal Firq =
Pparb =
Low-Power Stop
Freeze
Programming Model
SIM40 Programming Model
Mbar
Mbar
System Configuration and Protection Registers
MCR
SHENx Control Bits
SHEN1 SHEN0 Action
RSR
Sypcr
Swiv
See 4.2.2.5 Software Watchdog for more information
Deriving Software Watchdog Timeout
Software Timeout Period Crystal Period Clock Period
For more information see 4.2.2.2 Internal Bus Monitor
MHz External
BMTx Encoding
Picr
Pirql Encoding
Interrupts by Sources in the SIM40 for the servicing order
Pitr
Clock Synthesizer Control Register Syncr
Syncr
Chip Select Registers
Base Address $046, $04E, $056, $05E
Address Mask $042, $04A, $052, $05A
10. DDx Encoding
11. PSx Encoding
Response
Mode
External Bus Interface Control
Porta
$01F
PORTB, PORTB1
MC68340 Initialization Sequence
2 SIM40 Module Configuration
Startup
Freescale Semiconductor, Inc
Sspinit EQU
Mbar EQU
Modbase EQU $FFFFF000
MCR EQU
MOVEQ.L
MOVEC.L D0,DFC
MOVE.L #MODBASE+1,D0
MOVES.L D0,MBAR
CSAM0$ DC.L $0001FFFD
END
Section CPU32
Overview
Freescale Semiconductor, Inc Features
Virtual Memory
Loop Mode Instruction Execution
CPU32 Block Diagram
Vector Base Register
Exception Handling
Freescale Semiconductor, Inc Addressing Modes
Instruction Set
BFFFO, BFINS, BFSET, Bftst
CAS, CAS2
Instruction Set
Mnemonic Description
Processing States
Privilege States
Architecture Summary
Programming Model
User Programming Model
Freescale Semiconductor, Inc Registers
Status Register
Instruction SET
1 M68000 Family Compatibility
Instruction Format and Notation
Instruction Word General Format
Example d 16 is a 16-bit displacement
CCR
SSP
USP
DFC
Freescale Semiconductor, Inc Instruction Summary
Instruction Set Summary
Opcode Operation Syntax
Opcode Operation
Extb Llegal
Source ⇒ Destination Movep Dx,d,Ay Movep d,Ay,Dx
Instruction Set Summary Concluded
ROXL,ROXR
Condition Code Computations
Operations Special Definition
Data Movement Operations
Instruction Syntax
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Integer Arithmetic Operations
DIVS/DIVU
Logic Operations
Shift and Rotate Operations
Bit Manipulation Operations
Binary-Coded Decimal Operations
10. Program Control Operations
Conditional
Unconditional
Freescale Semiconductor, Inc
11. System Control Operations
Privileged
Trap Generating
Condition Code Register
12. Condition Tests
Using the TBL Instructions
Mnemonic Condition Encoding
13. Standard Usage Entries
Entry Number Value
Table Example 2 Compressed TABLE. In Example 2 see -8,
14. Compressed Table Entries
Table Example 15 -Bit Independent Variable Entries
Subroutine Instruction
Following value has been calculated for independent variable
Summing, the following result is obtained
Pipeline Synchronization with the NOP Instruction
Nested Subroutine Calls
Processing States
Freescale Semiconductor, Inc State Transitions
Privilege Levels
Exception Processing
Freescale Semiconductor, Inc Exception Vectors
16. Exception Vector Assignments
Vector Number Dec Hex
Assignment
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10. Exception Stack Frame
Characteristics
Group Exception Priority Relative Priority Reset
17. Exception Priority Groups
Freescale Semiconductor, Inc
11. Reset Operation Flowchart
Freescale Semiconductor, Inc
46MC68340 USER’S Manualmotorola
Freescale Semiconductor, Inc
Lpstop
Reset RTE Stop
Move USP Movec Moves
18. Tracing Control
Tracing Function
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Freescale Semiconductor, Inc
Fault Recovery
Freescale Semiconductor, Inc
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SIZ Func
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Freescale Semiconductor, Inc
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Freescale Semiconductor, Inc
Freescale Semiconductor, Inc 4 CPU32 Stack Frames
12. Format $0-Four-Word Stack Frame
14. Internal Transfer Count Register
15. Format $C-BERR Stack for Prefetches and Operands
Development Support
1 CPU32 Integrated Development Support
18. In-Circuit Emulator Configuration
20. BDM Block Diagram
Source BDM Enabled BDM Disabled
19. BDM Source Summary
20. Polling the BDM Entry Source
Atemp
Freescale
21. CPU Generated Message Encoding
Encoding Data Message Type
22. Debug Serial I/O Block Diagram
23. Serial Interface Timing Diagram
24. Bkpt Timing for Single Bus Cycle
25. Bkpt Timing for Forcing BDM
22. Size Field Encoding
BDM
Encoding Operand Size
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27. Command-Sequence Diagram
23. BDM Command Summary
Command
WDREG/WAREG
24. Register Field for Rsreg and Wsreg
System Register Select Code
MS Addr
Operand Data
Dump Long
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Write Memory Location XXX Not Ready Next CMD CMD Complete
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Chkstat MOVE.B SRA,D0
Command Format Command Sequence
Deterministic Opcode Tracking
28. Functional Model of Instruction Pipeline
29. Instruction Pipeline Timing Diagram
Instruction Execution Timing
Resource Scheduling
30. Block Diagram of Independent Resources
31. Simultaneous Instruction Execution
32. Attributed Instruction Times
Freescale Semiconductor, Inc
Instruction Stream Timing Examples
Instructions
33. Example 1-Instruction Stream
35. Example 2-Branch Not Taken
BRA.W Faraway MOVE.L
Instruction Timing Tables
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Instruction Head Tail Cycles
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Instruction
Head Tail Cycles
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DIVU.W
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#, Dn 20/1/0
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〈CEA 〉 40/1/x
Clocks Shift Counts
#, Dn 60/2/0
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BSR.B BSR.W BSR.L CHK
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Berr on instruction
Section DMA Controller Module
DMA Module Overview
Single-Address Transfers
DMA Module Signal Definitions
Transfer Request Generation
External Request Generation
Single-Address Mode
Data Transfer Modes
Freescale Semiconductor, Inc
Single-Address Read Timing External Burst
Single-Address Read Timing Cycle Steal
Single-Address Write Timing External Burst
Single-Address Write Timing Cycle Steal
Freescale Semiconductor, Inc Dual-Address Mode
Dual-Address Read Timing External Burst-Source Requesting
10. Dual-Address Read Timing Cycle Steal-Source Requesting
MOTOROLAMC68340 USER’S MANUAL6
Inc
CPU Cycle DMA Read
DMA Channel Operation
Channel Initialization and Startup
Data Transfers
Channel Termination
13. Fast Termination Option Cycle Steal
Register Description
14. Fast Termination Option External Burst-Source Requesting
Module Configuration Register MCR
15. DMA Module Programming Model
FRZx Control Bits
MCR1, MCR2
Action
Freescale Semiconductor, Inc
Channel Control Register CCR
Interrupt Register Intr
INTR1, INTR2
CCR1, CCR2
SSIZEx Encoding
Bit Definition
DSIZEx Encoding
REQx Encoding
BBx Encoding and Bus Bandwidth
REQ Field BB Field Bus Bandwidth Bit Definition
Channel Status Register CSR
CSR1, CSR2
Freescale Semiconductor, Inc
Freescale Semiconductor, Inc Function Code Register FCR
FCR1, FCR2
Destination Address Register DAR
Freescale Semiconductor, Inc Source Address Register SAR
SAR1, SAR2
DAR1, DAR2
Byte Transfer Counter Register BTC
BTC1, BTC2
Data Packing
16. Packing and Unpacking of Operands
DMA Channel Configuration
DMA Channel Initialization Sequence
Freescale Semiconductor, Inc
DMACH1 EQU
DMA Channel Example Configuration Code
DMAMCR1 EQU
DMAINT1 EQU
DMACCR1 EQU
DMACSR1 EQU
DMAFCR1 EQU
Daradd EQU
LEA
MOVE.L DARADD,DMADAR1A0
MOVE.B #$DD,DMAFCR1A0
MOVE.W #$0E8D,DMACCR1A0 END
MOVE.W
MOVE.W #$068D,DMACCR1A0 END
Modbase EQU
$6001 Source address is an ODD address
MOVE.W #$1DB1,DMACCR1A0 END
Section Serial Module
Local Loopback -Remote Loopback
Internal Channel Control Logic
Baud Rate Generator Logic
Interrupt Control Logic
Serial Module Signal Definitions
Comparison of Serial Module to MC68681
Crystal Input or External Clock
Crystal Output
Freescale Semiconductor, Inc External Input Sclk
Channel a Transmitter Serial Data Output TxDA
Channel a Receiver Serial Data Input RxDA
Channel B Transmitter Serial Data Output TxDB
Channel a Clear-To-Send Ctsa
Channel B Clear-To-Send Ctsb
Channel a Transmitter Ready T≈RDYA
Channel a Receiver Ready R≈RDYA
Baud Rate Generator
Operation
Transmitter and Receiver Operating Modes
Transmitter and Receiver Functional Diagram
Transmitter Timing Diagram
MOTOROLAMC68340 USER’S MANUAL7
Receiver Timing Diagram
Freescale Semiconductor, Inc
Freescale Semiconductor, Inc Looping Modes
Multidrop Mode
Looping Modes Functional Diagram
Multidrop Mode Timing Diagram
Register Description and Programming
Register Description
18MC68340 USER’S Manualmotorola
Serial Module Programming Model
FRZx Control Bits
Freeze
ILR
IVR
MR1A, MR1B
Parity Mode Parity Type
PMx and PT Control Bits
B/Cx Control Bits
SRA, SRB
Freescale Semiconductor, Inc
RCSx Control Bits
CSRA, Csrb
Set
TCSx Control Bits
CRA, CRB
MISCx Control Bits
MISC3 MISC2 MISC1 MISC0
TCx Control Bits
RCx Control Bits
RBA, RBB
TBA, TBB
Ipcr
ACR
ISR
Freescale Semiconductor, Inc
IER
$71D
Opcr
Bit Reset
Bit Set
MR2A, MR2B
CMx Control Bits
10. SBx Control Bits
Length 6-8 Bits Length 5 Bits
Freescale Semiconductor, Inc Programming
10. Serial Module Programming Flowchart 1
10. Serial Module Programming Flowchart 2
10. Serial Module Programming Flowchart 3
10. Serial Module Programming Flowchart 4
10. Serial Module Programming Flowchart 5
Serial Module Configuration
Serial Module Initialization Sequence
Serial Module Example Configuration Code
Serial EQU
Mcrh EQU
Mcrl EQU
Wait for Transmitter Empty or Timeout MOVE.W
Negate Rtsa Signal Output MOVE.B
Reset RECEIVER/TRANSMITTER MOVE.B
Mode Register MOVE.B
Mode Register
SET UP Baud Rate for Port in Clock Select Register
Enable Port
MOVE.B #$BB,CSRAA0
Section Timer Modules
Timer and Counter Functions
Timer Functional Diagram
Internal Control Logic
Timer Modules Signal Definitions
Freescale Semiconductor, Inc Interrupt Control Logic
Timer Input TIN1, TIN2
External and Internal Interface Signals
Timer Gate TGATE1, TGATE2
Timer Output TOUT1, TOUT2
Operating Modes
Input Capture/Output Compare
TGATE≈
Square-Wave Generator Mode
Square-Wave Generator
Variable Duty-Cycle Square-Wave Generator
Variable Duty-Cycle Square-Wave Generator Mode
Variable-Width Single-Shot Pulse Generator
Variable-Width Single-Shot Pulse Generator Mode
Pulse-Width Measurement Mode
Pulse-Width Measurement
Period Measurement
Period Measurement Mode
Event Count
10. Event Count Mode
Freescale Semiconductor, Inc Timer Bypass
OCx Encoding
OC1 OC0 TOUTx
11. Timer Module Programming Model
FRZ1 FRZ0 Action
Freescale Semiconductor, Inc Interrupt Register IR
Control Register CR
Enabled Interrupts
IEx Encoding
TOUTx Mode
POT Encoding
MODEx Encoding
Division
Status Register SR
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Preload 1 Register PREL1
Counter Register Cntr
Cntr
Preload 2 Register PREL2
Compare Register COM
PREL1
PREL2
Timer Module Initialization Sequence
Timer Module Configuration
Timer Module Example Configuration Code
CLR.W COM1A0
END
BNE.B LOOP1
BEQ.B LOOP2
BEQ.B LOOP3
MOVE.W CNTR1A0,D0 NOT.W D0 ADDQ.W #$1,DO
Section Ieee 1149.1 Test Access Port
Non-IEEE 1149.1 Operation for details
Test Access Port Block Diagram
TAP Controller
Boundary Scan Register
TAP Controller State Machine
Boundary Scan Control Bits
Name Bit Number
Boundary Scan Bit Definitions
Pin/Cell Output
Pin/Cell Output Num Cell Type
Type CTL Cell Num Cell Type
Pin/Cell Output Bit Num Cell Type
Ipipe
Freescale Semiconductor
Active-High Output Control Cell IO.Ctl1
Instruction Register
Bidirectional Data Cell IO.Cell
SAMPLE/PRELOAD
Extest
Code Instruction
HI-Z
Bypass X1X
MC68340 Restrictions
NON-IEEE 1149.1 Operation
Minimum System Configuration
Processor Clock Circuitry
Sample Crystal Circuit
Reset Circuitry
Sram Interface
ROM Interface
Serial Interface
Using an 8-Bit Boot ROM
Memory Interface Information
Access Time Calculations
Bit Boot ROM Timing
Memory Access Times at 16.78 MHz
Calculating Frequency-Adjusted Output
Access Time
12. Signal Width Specifications
13. Skew between Two Outputs
Power Consumption Considerations
CD-I, CD-ROM
15. MC68340 Current vs. Activity at 5
16. MC68340 Current vs. Voltage/Temperature
Typical Electrical Characteristics
Freescale Semiconductor, Inc 10.3.2 MC68340V 3.3
Parameter
Advantage Benefit
Thermal Characteristics
Rating Symbol Value Unit
Characteristic Symbol Value Unit
Maximum Ratings
Power Considerations
AC Electrical Specification Definitions
Pint + PI/O
PI/O
MOTOROLAMC68340 USER’S MANUAL11-3
Drive Levels and Test Points for AC Specifications
Characteristic Symbol Min Max Unit
CLKOUT, FREEZE, IPIPE, Ifetch
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MOTOROLAMC68340 USER’S MANUAL11-7
Num.Characteristic
39 MHz 16.78 MHz 25.16 MHz Symbol Min Max Unit
Freescale Semiconductor, Inc AC Timing Specifications
25.16 MHz Num Characteristic Symbol Min Max Unit
Num Characteristic Symbol Min Max
39 MHz 16.78 MHz
Read Cycle Timing Diagram
Write Cycle Timing Diagram
Fast Termination Read Cycle Timing Diagram
Fast Termination Write Cycle Timing Diagram
Bus Arbitation Timing-Active Bus Case
Bus Arbitration Timing-Idle Bus Case
Iack Cycle Timing Diagram
10. Background Debug Mode Serial Port Timing
25.16 MHz Num Characteristic Min Max
Or 5.0 39 MHz
13. Timer Module Clock Signal Timing Diagram
Min Max Unit
Freescale
15. Serial Module General Timing Diagram
16. Serial Module Asynchronous Mode Timing
19. Test Clock Input Timing Diagram
20. Boundary Scan Timing Diagram
Section Ordering Information and Mechanical Data
Standard MC68340 Ordering Information
12-2MC68340 USER’S Manualmotorola
Pin Group FE Suffix
VCC GND
12-4MC68340 USER’S Manualmotorola
Pin Group RP Suffix
12-6
Freescale Semiconductor, Inc RP Suffix
DIM MIN MAX
D E
CTS
Dsack
Index-4
USER’S Manual
Freescale Semiconductor, Inc
Motorola MC68340 USER’S Manual
Index-8
Index-9
