Freescale Semiconductor, Inc.

5.7.3.3MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock periods needed for the processor to calculate the destination EA and to perform a MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate that portion of the instruction time.

Destination EAs are divided by their formats (see 5.3.4.4 Effective Address Encoding Summary). The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

When using this table, begin at the top and move downward. Use the first entry that matches both source and destination addressing modes.

Semiconductor, Inc...

Instruction

MOVE Rn, Rn

MOVE 〈FEA〉 , Rn

MOVE Rn, (Am)

MOVE Rn, (Am) +

MOVE Rn, −(Am)

MOVE Rn, 〈CEA 〉

MOVE 〈FEA〉 , (An)

MOVE 〈FEA〉 , (An) +

MOVE 〈FEA〉 , −(An)

MOVE #, 〈CEA〉

MOVE 〈CEA〉 , 〈FEA 〉

Head

Tail

Cycles

0

0

2(0/1/0)

0

0

2(0/1/0)

0

2

4(0/1/x)

1

1

5(0/1/x)

2

2

6(0/1/x)

1

3

5(0/1/x)

2

2

6(0/1/x)

2

2

6(0/1/x)

2

2

6(0/1/x)

2

2

6(0/1/x) ∗

2

2

6(0/1/x)

Freescale

X = There is one bus cycle for byte and word operands and two bus cycles for long-word operands. For long-word bus cycles, add two clocks to the tail and to the number of cycles.

∗= An # fetch EA time must be added for this instruction: 〈 FEA 〉 +〈CEA〉 + 〈 OPER〉

NOTE: For instructions not explicitly listed, use the MOVE 〈CEA 〉, 〈FEA〉 entry. The source EA is calculated by the calculate EA table, and the destination EA is calculated by the fetch EA table, even though the bus cycle is for the source EA.

5.7.3.4SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch, calculate, and perform the special-purpose MOVE operation on control registers or a specified EA. Footnotes indicate when to account for the appropriate EA times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

MOTOROLAMC68340 USER’S MANUAL5- 101

For More Information On This Product,

Go to: www.freescale.com

Page 237 Page 239
Page 238
Image 238
Motorola MC68340 manual Instruction, Head Tail Cycles
Page 237 Page 239

MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
Top Page Image Contents