Bkpt Timing for Single Bus Cycle | Motorola MC68340 guide

Freescale Semiconductor, Inc.

SHIFT_CLK

FORCE_BGND

BKPT_TAG

.BKPT. ...... . . . ... . . . .

FREEZE

Figure 5-24. BKPT Timing for Single Bus Cycle

Figure 5-25 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock is left high after the final shift of each transfer. This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BDM session. As mentioned previously, all timing within the CPU is derived from the rising edge of the clock; the falling edge is effectively ignored.

SHIFT_CLK

FORCE_BGND

BKPT_TAG

.BKPT. ...... . . . ... . . ... .

FREEZE

Figure 5-25. BKPT Timing for Forcing BDM

Figure 5-26 represents a sample circuit providing for both BKPT assertion methods. As the name implies, FORCE_BGND is used to force a transition into BDM by the assertion of BKPT. FORCE_BGND can be a short pulse or can remain asserted until FREEZE is asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT_CLK is applied.

BKPT_TAG

SHIFT. . ._CLK

RESET

FORCE_BGND

S1 Q

BKPT/DSCLK

Figure 5-26. BKPT/DSCLK Logic Diagram

BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the first

DSCLK.

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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.

Motorola MC68340 manual Bkpt Timing for Single Bus Cycle, Bkpt Timing for Forcing BDM

Models: MC68340

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Figure 5-24. BKPT Timing for Single Bus Cycle

Figure 5-25. BKPT Timing for Forcing BDM

Figure 5-26. BKPT/DSCLK Logic Diagram

MC68340 specifications