Motorola MC68340 manual Ivr, MR1A, MR1B

Models: MC68340

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

IVR

 

 

 

 

 

 

$705

7

6

5

4

3

2

1

0

IVR7

IVR6

IVR5

IVR4

IVR3

IVR2

IVR1

IVR0

RESET:

 

 

 

 

 

 

 

0

0

0

0

1

1

1

1

Read /Write

 

 

 

Supervisor Only

IVR7–IVR0—Interrupt Vector Bits

Each module that generates interrupts has an interrupt vector field. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IVR is reset to $0F, which indicates an uninitialized interrupt condition. See Section 5 CPU32 for more information.

7.4.1.4MODE REGISTER 1 (MR1). MR1 controls some of the serial module configuration. This register can be read or written at any time when the serial module is enabled (i.e., the STP bit in the MCR is cleared).

MR1A, MR1B

 

 

 

$710, $718

7

6

5

4

3

2

1

0

RxRTS

R/F

ERR

PM1

PM0

PT

B/C1

B/C0

RESET:

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

Read/WriteSupervisor/User

RxRTS—Receiver Request-to-Send Control

1 = Upon receipt of a valid start bit, RTSis negated if the channel's FIFO is full. RTSis reasserted when the FIFO has an empty position available.

0 = RTSis asserted by setting bit 1 or 0 in the OP and negated by clearing bit 1 or 0 in the OP.

This feature can be used for flow control to prevent overrun in the receiver by using the RTSoutput to control the CTSinput of the transmitting device. If both the receiver and transmitter are programmed for RTS control, RTS control will be disabled for both since this configuration is incorrect. See 7.4.1.17 Mode Register 2 for information on programming the transmitter RTScontrol.

R/F—Receiver-Ready Select

1 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel FIFO full

status. These ISR bits are set when the receiver FIFO is full and are cleared when a position is available in the FIFO.

0 = Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiver- ready status. These ISR bits are set when a character has been received and are cleared when the CPU32 reads the receive buffer.

7- 22MC68340 USER’S MANUALMOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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Motorola MC68340 manual Ivr, MR1A, MR1B

MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.