Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

5.7.3.10BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

 

Instruction

Head

Tail

Cycles

BCHG

#, Dn

2

0

∗

 

 

6(0/2/0)

BCHG

Dn, Dm

4

0

6(0/1/0)

BCHG

#, 〈FEA〉

1

2

∗

 

 

8(0/2/1)

BCHG

Dn, 〈FEA 〉

2

2

8(0/1/1)

BCLR

#, Dn

2

0

∗

 

 

6(0/2/0)

BCLR

Dn, Dm

4

0

6(0/1/0)

BCLR

#, 〈FEA〉

1

2

∗

 

 

8(0/2/1)

BCLR

Dn, 〈FEA 〉

2

2

8(0/1/1)

BSET

#, Dn

2

0

∗

 

 

6(0/2/0)

BSET

Dn, Dm

4

0

6(0/1/0)

BSET

#, 〈FEA〉

1

2

∗

 

 

8(0/2/1)

BSET

Dn, 〈FEA 〉

2

2

8(0/1/1)

BTST

#, Dn

2

0

∗

 

 

4(0/2/0)

BTST

Dn, Dm

2

0

4(0/1/0)

BTST

#, 〈FEA〉

1

0

∗

 

 

4(0/2/0)

BTST

Dn, 〈FEA 〉

2

0

8(0/1/0)

∗ = An # fetch EA time must be added for this instruction: 〈 FEA 〉 + 〈FEA 〉 + 〈OPER 〉

MOTOROLAMC68340 USER’S MANUAL5- 109

For More Information On This Product,

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Motorola MC68340 manual #, Dn 60/2/0
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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