Motorola MC68340 manual External Request Generation

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

6.3.1.1INTERNAL REQUEST, MAXIMUM RATE. Internal generation using 100% of the internal bus always has a transfer request pending for the channel until the transfer is complete. As soon as the channel is started, the DMA will arbitrate for the internal bus and begin to transfer data when it becomes bus master. If no exceptions occur, all operands in the data block will be transferred in one burst so that the DMA will use 100% of the available bus bandwidth.

6.3.1.2INTERNAL REQUEST, LIMITED RATE. To guarantee that the DMA will not use all of the available bus bandwidth during a transfer, internal requests can be generated according to the amount of bus bandwidth allocated to the DMA. There are three programmed constants in the CCR used to monitor the bus activity and allow the DMA to use a percentage of the bus bandwidth. Options are 25%, 50%, and 75% of 1024 clock periods. See Table 6-5 for more information.

6.3.2 External Request Generation

To control the transfer of operands to or from memory in an orderly manner, a peripheral device uses the DREQ≈ input signal to request service. If the channel is programmed for external request and the CCR STR bit is set, an external request (DREQ≈) signal must be asserted before the channel requests the bus and begins a transfer. The DMA supports external burst mode and external cycle steal mode.

The generation of the request from the source or destination is specified by the ECO bit of the CCR. The external requests can be for either single- or dual-address transfers.

6.3.2.1EXTERNAL BURST MODE. For external devices that require very high data

transfer rates, the burst request mode allows the DMA channel to use all of the bus bandwidth under control of the external device. In burst mode, the DREQ≈ input to the

DMA is level sensitive and is sampled at certain points to determine when a valid request is asserted by the device. The device requests service by asserting DREQ≈ and leaving it

asserted. In response, the DMA arbitrates for the bus and performs an operand transfer. During each operand transfer, the DMA asserts DMA acknowledge (DACK≈) to indicate to the device that a request is being serviced. DACK≈ is asserted on the cycle of either the source or destination device, depending on which one generated the request as programmed by the CCR ECO bit.

To allow more than one transfer to be recognized, DREQ≈ must meet the asynchronous setup and hold times while DACK≈ is asserted in the DMA bus cycle. Upon completion of a request, DREQ≈ should be held asserted (bursting) into the following DMA bus cycle to allow another transfer to occur. The recognized request will immediately be serviced. If DREQ≈ is negated before DACK≈ is asserted, a new request is not recognized, and the DMA channel releases ownership of the bus.

6.3.2.2EXTERNAL CYCLE STEAL MODE. For external devices that generate a pulsed signal for each operand to be transferred, the cycle steal request mode uses the DREQ≈ signal as a falling-edge-sensitive input. The DREQ≈ pulse generated by the device must be asserted during two consecutive falling edges of the clock to be recognized as valid.

MOTOROLAMC68340 USER’S MANUAL6- 5

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