Motorola MC68340 manual Signal Index, Input, Signal Name Mnemonic Function Output

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

2.1 SIGNAL INDEX

The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the signal paragraph. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in Section 11 Electrical Characteristics .

Table 2-1. Signal Index

			Input/
Signal Name	Mnemonic	Function	Output
Address Bus	A23–A0	Lower 24 bits of the address bus	Out
Address Bus/Port A7–A0/	A31–A24	Upper eight bits of the address bus, parallel I/O port, or	Out/I/O/Out
Interrupt Acknowledge		interrupt acknowledge lines
Data Bus	D15–D0	The 16-bit data bus used to transfer byte or word data	I/O
Function Codes	FC3–FC0	Identify the processor state and the address space of the	Out
		current bus cycle
Chip Select 3–1/	CS3–CS1	Enables peripherals at programmed addresses, interrupt	Out/In/
Interrupt Request Level/		priority level to the CPU32, or parallel I/O port	I/O
Port B4, B2, B1
Chip Select 0/Autovector	CS0	Enables peripherals at programmed addresses or	Out/In
		requests an automatic vector
Bus Request	BR	Indicates that an external device requires bus mastership	In
Bus Grant	BG	Indicates that current bus cycle is complete and the	Out
		MC68340 has relinquished the bus
Bus Grant Acknowledge	BGACK	Indicates that an external device has assumed bus	In
		mastership
Data and Size	DSACK1,	Provides asynchronous data transfers and dynamic bus	In
Acknowledge	DSACK0	sizing
Read-Modify-Write Cycle	RMC	Identifies the bus cycle as part of an indivisible read -	Out
		modify-write operation
Address Strobe	AS	Indicates that a valid address is on the address bus	Out
Data Strobe	DS	During a read cycle, DS indicates that an external device	Out
		should place valid data on the data bus. During a write
		cycle, DS indicates that valid data is on the data bus.
Size	SIZ1, SIZ0	Indicates the number of bytes remaining to be transferred	Out
		for this cycle
Read/Write	R/ W	Indicates the direction of data transfer on the bus	Out
Interrupt Request Level/	IRQ7, IRQ6,	Provides an interrupt priority level to the CPU32 or	In/I/O
Port B7, B6, B5, B3	IRQ5, IRQ3	becomes a parallel I/O port
Reset	RESET	System reset	I/O
Halt	HALT	Suspends external bus activity	I/O
Bus Error	BERR	Indicates an invalid bus operation is being attempted	In
System Clock	CLKOUT	System clock out	Out
Crystal Oscillator	EXTAL, XTAL	Connections for an external crystal or oscillator to the	In, Out
		internal oscillator circuit
External Filter Capacitor	XFC	Connection pin for an external capacitor to filter the circuit	In
		of the phase-locked loop

2- 2MC68340 USER’S MANUALMOTOROLA

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