Motorola MC68340 manual Interrupt Acknowledge Cycle Flowchart

Models: MC68340

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The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in

3.3.1Read Cycle in that it accesses the CPU address space. Specifically, the differences are as follows:

1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space.

2.A3, A2, and A1 are set to the interrupt request level, and the IACKstrobe

corresponding to the current interrupt level is asserted. (Either the function codes and address signals or the IACKstrobes can be monitored to determine that an interrupt acknowledge cycle is in progress and the current interrupt level.)

3.The CPU32 space type field (A19–A16) is set to $F (interrupt acknowledge).

4.Other address signals (A31–A20, A15–A4, and A0) are set to one.

5.The SIZ0/SIZ1 and R/W signals are driven to indicate a single-byte read cycle. The responding device places the vector number on the least significant byte of its data port (for an 8-bit port, the vector number must be on D15–D8; for a

16-bit port, the vector must be on D7–D0) during the interrupt acknowledge cycle. The cycle is then terminated normally with DSACK.

Figure 3-14 is a flowchart of the interrupt acknowledge cycle; Figure 3-15 shows the timing for an interrupt acknowledge cycle terminated with DSACK.

Freescale Semiconductor,

INTERRUPTING DEVICE

REQUEST INTERRUPT

PROVIDE VECTOR NUMBER

1.PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA BUS

2.ASSERT DSACKx (OR AVEC IF NO VECTOR NUMBER)

RELEASE

1. NEGATE DSACKx

MC68340

GRANT INTERRUPT

1.SYNCHRONIZE IRQ7–IRQ1

2.COMPARE IRQ1–IRQ7 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE

3.PLACE INTERRUPT LEVEL ON A3–A1; TYPE FIELD (A19–A16) = $F

4.SET R/W TO READ

5.SET FC3–FC0 TO 0111

6.DRIVE SIZE PINS TO INDICATE A ONE-BYTE TRANSFER

7.ASSERT AS AND DS

8.ASSERT THE CORRESPONDING IACKx STROBE.

ACQUIRE VECTOR NUMBER

1.LATCH VECTOR NUMBER

2.NEGATE DS AND AS

START NEXT CYCLE

Figure 3-14. Interrupt Acknowledge Cycle Flowchart

3- 28MC68340 USER’S MANUALMOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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Motorola MC68340 manual Interrupt Acknowledge Cycle Flowchart

MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.