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Motorola MC68340 manual Freescale Semiconductor, Inc Bus Request, Bus Grant Acknowledge

Models: MC68340

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

3.6.1 Bus Request

External devices capable of becoming bus masters request the bus by asserting BR. This signal can be wire-ORed to indicate to the MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no BGACK is received while the BR is active, the MC68340 remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership.

3.6.2 Bus Grant

The MC68340 supports operand coherency; thus, if an operand transfer requires multiple bus cycles, the MC68340 does not release the bus until the entire transfer is complete. Therefore, assertion of BG is subject to the following constraints:

•The minimum time for BG assertion after BR is asserted depends on internal synchronization (see Section 11 Electrical Characteristics ).

•During an external operand transfer, the MC68340 does not assert BG until after the last cycle of the transfer (determined by SIZx and DSACK≈).

•During an external operand transfer, the MC68340 does not assert BG as long as RMC is asserted.

•If the show cycle bits SHEN1–SHEN0 = 01, the MC68340 does not assert BG to an external master.

Externally, the BG signal can be routed through a daisy-chained network or a priority- encoded network. The MC68340 is not affected by the method of arbitration as long as the protocol is obeyed.

3.6.3 Bus Grant Acknowledge

An external device cannot request and be granted the external bus while another device is the active bus master. A device that asserts BGACK remains the bus master until it negates BGACK. BGACK should not be negated until all required bus cycles are completed. Bus mastership is terminated at the negation of BGACK.

Once an external device receives the bus and asserts BGACK, it should negate BR. If BR remains asserted after BGACK is asserted, the MC68340 assumes that another device is requesting the bus and prepares to issue another BG.

MOTOROLAMC68340 USER’S MANUAL3- 43

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Motorola MC68340 manual Freescale Semiconductor, Inc Bus Request, Bus Grant Acknowledge
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.