Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

3.5 BUS EXCEPTION CONTROL CYCLES

The bus architecture requires assertion of DSACK≈ from an external device to signal that a bus cycle is complete. Neither DSACK≈ nor AVEC is asserted in the following cases:

•DSACK≈/AVEC is programmed to respond internally.

•The external device does not respond.

•Various other application-dependent errors occur.

The MC68340 provides BERR when no device responds by asserting DSACK≈/AVEC within an appropriate period of time after the MC68340 asserts AS. This mechanism allows the cycle to terminate and the MC68340 to enter exception processing for the error condition. HALT is also used for bus exception control. This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation, or, in combination with BERR, a retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus error condition, DSACK≈, BERR, and HALT can be asserted and negated with the rising edge of the MC68340 clock. This assures that when two signals are asserted simultaneously, the required setup and hold time for both is met for the same falling edge of the MC68340 clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK≈ assertion as follows (case numbers refer to Table

3-4):

•Normal Termination: DSACK≈ is asserted; BERR and HALT remain negated (case 1).

•Halt Termination: HALT is asserted at the same time as or before DSACKx, and BERR remains negated (case 2).

•Bus Error Termination: BERR is asserted in lieu of, at the same time as, or before DSACK≈ (case 3) or after DSACK≈ (case 4), and HALT remains negated; BERR is negated at the same time as or after DSACK≈.

•Retry Termination: HALT and BERR are asserted in lieu of, at the same time as, or before DSACK≈ (case 5) or after DSACK≈ (case 6); BERR is negated at the same time as or after DSACK≈, and HALT may be negated at the same time as or after BERR.

Table 3-4 lists various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to the specifications given in Section 11 Electrical Characteristics . DSACK≈ BERR, and HALT may be negated after AS. If DSACK≈ or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely.

EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3).

3- 32MC68340 USER’S MANUALMOTOROLA

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Motorola MC68340 manual BUS Exception Control Cycles
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MC68340 specifications

The Motorola MC68340 is a highly integrated microprocessor that was introduced in the early 1990s. It belongs to the 68000 family of microprocessors and is designed to cater to the demands of embedded systems, particularly in telecommunications and networking applications. This chip represents a significant evolution in microprocessor technology by combining a microprocessor core with additional peripherals on a single chip, making it an attractive solution for engineers looking to design compact and efficient systems.

One of the key features of the MC68340 is its 32-bit architecture, which allows for significant processing power and data handling capabilities. This architecture enables the processor to handle larger data sizes and perform more complex calculations compared to its 16-bit predecessors. The MC68340 operates at clock speeds typically ranging from 16 MHz to 25 MHz. Its dual instruction pipeline enhances throughput, allowing for simultaneous instruction fetches and executions, which significantly boosts performance.

A notable characteristic of the MC68340 is the inclusion of integrated peripherals, which help reduce the overall component count in a system. Key integrated components include a memory management unit (MMU), a direct memory access (DMA) controller, and various communication interfaces such as serial ports. The memory management capabilities enhance the processor's ability to manage memory resources efficiently, enabling it to support multitasking environments commonly found in modern computing.

In terms of connectivity, the MC68340 features connections for both synchronous and asynchronous serial communication, making it well-suited for networking tasks. The processor supports a range of bus standards, including address and data buses, which facilitate seamless interaction with peripheral devices.

Another important aspect of the MC68340 is its flexibility. The processor supports multiple operating modes, including multiple CPU configurations and compatibility with the Motorola 68000 family, allowing for easier integration into existing systems.

Moreover, the MC68340 boasts low power consumption compared to many of its contemporaries, making it an excellent choice for battery-operated applications, enhancing its appeal in sectors like telecommunications, industrial control, and automotive systems. Its combination of performance, integration, versatility, and efficiency has secured the MC68340 a reputable position in the annals of embedded systems technology, proving to be a valuable asset for developers and engineers alike.
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