Motorola MC68340 manual Dual-Address Read Timing Cycle Steal-Source Requesting

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

DMA WRITE	S2 S4
	S0
READ	S4
	S2
DMA
	S0
CPU CYCLE	S2 S4
	S0
WRITE	S4
DMA	S2
	S0
READ	S4
DMA	S2
	S0
CPU CYCLE	S2 S4
	S0
CPU CYCLE	S2 S4
	S0

CLKOUT A31–A0 FC3–FC0 SIZ1–SIZ0 AS DS R/W D15–D0 DSACKx DREQx DONEx (INPUT) DACKx DONEx (OUTPUT) NOTE

be recognized.		asserted and before DACKx is negated.
for two consecutive clocks for a DMA request to		transfer, the DREQx is asserted after DACKx is
DREQx must be active		To cause another DMA
1.	2.

3. DACKx and DONEx (DMA control signals) are asserted in the source (read) DMA cycle.

4. DONEx (input) can be asserted in either the read or write DMA bus cycle to indicate that the next DMA transfer will be the last one.

Figure 6-10. Dual-Address Read Timing (Cycle Steal–Source Requesting)

6.4.2.2DUAL-ADDRESS WRITE. During the dual-address write cycle, the DMA writes data to a device or memory from the internal DHR. The data in the DHR is written to the device or memory selected by the address in the DAR, the destination function codes in

6- 14MC68340 USER’S MANUALMOTOROLA

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