Document No. X27A-Q-001-04
S1D13705
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Customer Support Information
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February
S1D13705 Embedded Memory LCD Controller
Embedded 80K byte Sram display buffer
Software Suspend mode LCD power-down sequencing
Document Number X27A-A-001-10
Hardware Functional Specification
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Table of Contents
Mechanical Data
Power Save Modes
Registers
SwivelView
List of Tables
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List of Figures
2 Bit-per-pixel Monochrome Mode Data Output Path
Overview Description
Introduction
Scope
Display Support
Features
Integrated Frame Buffer
CPU Interface
Package
Display Modes
Clock Source
Miscellaneous
Typical System Diagram SH-4 Bus
Typical System Implementation Diagrams
Typical System Diagram M68K #1 Bus
Typical System Diagram Generic #1 Bus
Memory Controller
Functional Block Diagram
Functional Block Descriptions
Host Interface
LCD Interface
Power Save
Power Save contains the power save mode circuitry
Look-Up Table
Package type 80 pin surface mount QFP14
Pins
Pinout Diagram
Description
Pin Description
Key
Pin Names Type Pin # Cell
For the lower data byte WE0#
For SH-3/SH-4 mode, this pin inputs the write enable signal
Input This pin inputs the chip select signal
For MC68K #1, this pin inputs the R/W# signal
Pin Name Type Pin # Cell
Pin Name Type Pin # Driver Description
Power Supply
Clock Input
Miscellaneous
Host Bus Interface Pin Mapping
Summary of Configuration Options
Summary of Power On/Reset Options
Host Bus Interface Pin Mapping
Bit Pin Name Bit Dual Single 12-bit Format
LCD Interface Pin Mapping
LCD Interface Pin Mapping
Recommended Operating Conditions for Core VDD = 3.3V ± 10%
C. Characteristics
Input Specifications
Absolute Maximum Ratings
Output Specifications
1 SH-4 Interface Timing
Bus Interface Timing
T11 Rising edge CSn# to RDY# high impedance
Symbol Parameter Min Max Units
Bus Clock frequency MHz
Bus Clock period
Write T16 T17 D150
2 SH-3 Interface Timing
T12 T13
T14 T15 D150
Symbol Parameter Min Maxa Units
UDS#, LDS# falling edge to D150 valid write cycle
Motorola MC68K #1 Interface Timing
AS# high to DTACK# high AS# high to DTACK# high impedance
AS#, DS# rising edge to D3116 high impedance
Motorola MC68K #2 Interface Timing
AS# high to DSACK1# high AS# high to DSACK1# high impedance
DS# falling edge to D3116 valid write cycle
Generic #1 Timing
Generic #1 Interface Timing
Generic #2 Timing
Generic #2 Interface Timing
Input Clock Pulse Width High Clki
Clock Input Requirements
Input Clock Frequency Clki MHz
Input Clock period Clki
Input Clock Pulse Width High Bclk
Input Clock Frequency Bclk MHz
Input Clock period Bclk
REG03h to FPLINE, FPFRAME, FPSHIFT, FPDAT, Drdy
Power On/Reset Timing
Symbol Parameter Min Typ Max Units
Display Interface
Active Inactive
Power Down/Up Timing
Lcdpwr Override REG03h bit HW Power Save
REG03h bits FP Signals Active Inactive
11 Single Monochrome 4-Bit Panel Timing
Single Monochrome 4-Bit Panel Timing
Data Timing
Sync Timing
13 Single Monochrome 8-Bit Panel Timing
Single Monochrome 8-Bit Panel Timing
= REG08h bits 4-0 x 8 + 4Ts
15 Single Color 4-Bit Panel Timing
Single Color 4-Bit Panel Timing
= REG08h bits 4-0 x 8 + 1.5Ts
17 Single Color 8-Bit Panel Timing Format
Single Color 8-Bit Panel Timing Format
T6a T6b T7a T14 T11
19 Single Color 8-Bit Panel Timing Format
= REG08h bits 4-0 x 8 + 1Ts
21 Dual Monochrome 8-Bit Panel Timing
Dual Monochrome 8-Bit Panel Timing
= REG04h bits 6-0+1 x 8 + REG08h bits 4-0 + 4 x 8 x 2Ts
23 Dual Color 8-Bit Panel Timing
Dual Color 8-Bit Panel Timing
= REG08h bits 4-0 x 2x 8 + 17Ts
25 12-Bit TFT/D-TFD Panel Timing
10 9/12-Bit TFT/D-TFD Panel Timing
26 TFT/D-TFD A.C. Timing
18 TFT/D-TFD A.C. Timing
Bit
Registers
Register Mapping
Register Descriptions
Don’t care
Active high
Panel Data Format
Color/Mono Dual/Single Data Width Bit Function
High Performance BPP Bit Display Modes
Gray Scale/Color Mode Selection
Color/Mono Bit-Per-Pixel Bit Display Mode
High Performance Selection
Video data is inverted after the Look-Up Table
Video Mode Select Options below
Inverse Video Mode Select Options
Software Power Save Mode Selection
Hardware Power Save/GPIO0 Operation
Size Bit
This register must not be set to a value less than 03h
Vertical Panel
Fpline Start
Following constraint must be satisfied
MOD Rate Bit
Vertical Non
Screen 2 Start
Screen 1 Start
Vertical Size Bit
Memory
Offset Bit
LUT Address
Screen-Register Relationship, Split Screen
LUT Data Bit
REG18h Gpio Configuration Control Register
SwivelView Mode Enable Mode Select
Selection of SwivelView Mode
Where CLK is Clki REG02h bit 4 = 0 or CLKI/2 REG02h bit 4 =
Selection of Pclk and Mclk in SwivelView Mode
Create a virtual image in SwivelView mode
Pixel Clock Pclk Select Mode Enable Mode Select
TFT/D-TFD and Passive Single-Panel modes
Passive Dual-Panel mode
Frame Rate Calculation
1/2/4/8 Bit-Per-Pixel Display Data Memory Organization
Display Data Formats
Green Look-Up Table LUT is used for all monochrome modes
Bit-per-pixel Monochrome mode
Look-Up Table Architecture
Monochrome Modes
4 Bit-per-pixel Monochrome Mode Data Output Path
Color Modes
Bit-per-pixel Color Mode
2 Bit-per-pixel Color Mode Data Output Path
4 Bit-per-pixel Color Mode Data Output Path
8 Bit-per-pixel Color Mode Data Output Path
SwivelView
Default SwivelView Mode
Where bpb is bits-per-byte and bpp is bits-per-pixel
How to Set Up Default SwivelView Mode
Where bpp is bits-per-pixel and bpb is bits-per-byte
Start Address 480 Image refreshed by S1D13705
Alternate SwivelView Mode
How to Set Up Alternate SwivelView Mode
Default SwivelView Mode Alternate SwivelView Mode
Comparison Between Default and Alternate SwivelView Modes
SwivelView Mode Limitations
Default and Alternate SwivelView Mode Comparison
Hardware Power Save Mode
Power Save Modes
Software Power Save Mode
Hardware Software Normal
Power Save Mode Function Summary
Panel Power Up/Down Sequence
Power Save Mode Function Summary
Software Power Save
Turning Off Bclk Between Accesses
S1D13705 Internal Clock Requirements
Clock Requirements
125
Mechanical Data
QFP14 80 pin Unit mm
14.0 ± 12.0 ± Index
Japan North America Taiwan
Sales and Technical Support
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Document Number X27A-G-002-03
Programming Notes and Examples
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Look-Up Table LUT
LCD Power Sequencing and Power Save Modes
Introduction Initialization
Memory Models
Sample Code
Identifying the S1D13705 Hardware Abstraction Layer HAL
S1D13705 Initialization Sequence
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Introduction
Register Values
Initialization
Display Buffer Location
Register Value hex See Also
Frame Rate Calculation
S1D13705 Initialization Sequence
= Horizontal Non-Display Period in pixels
Where Pclk = Pixel clock in Hz
For a dual passive panel the formula is
= Horizontal Display Period in pixels
Epson Research and Development
Bit Pixel
Memory Models
1 Bit-Per-Pixel 2 Colors/Gray Shades
Pixel Bit
2 Bit-Per-Pixel 4 Colors/Gray Shades
4 Bit-Per-Pixel 16 Colors/Gray Shades
Green bit
Eight Bit-Per-Pixel 256 Colors
Look-Up Table LUT
LUT Data
Look-Up Table Registers
Unused entries
Look-Up Table Organization
Color Modes
Index Red Green Blue
Indicates unused entries
Example LUT Values for 2 Bpp Color Mode
Bpp color
Index
Index
Address Red Green Blue
Gray Shade Modes
Recommended LUT Values for 1 Bpp Gray Shade
Suggested Values for 2 Bpp Gray Shade
Suggested LUT Values for 4 Bpp Gray Shade
Virtual Display
Advanced Techniques
Offset
Registers
Examples
REG11h Memory Address Offset Register
Panning and Scrolling
REG10h Screen 1 Display Start Address 2 MSB
Number of Pixels Panned Using Start Address
REG0Ch Screen 1 Display Start Address 0 LSB
REG0Dh Screen 1 Display Start Address 1 MSB
Panning to the left
To scroll down
320x240 Single Panel For Split Screen
Split Screen
REG13 Screen 1 Vertical Size MSB
REG12 Screen 1 Vertical Size LSB
REG0Fh Screen 2 Display Start Address 1 MSB
REG0Eh Screen 2 Display Start Address 0 LSB
Examples
Hardware Software Power Save Override Enable Bit
LCD Power Sequencing and Power Save Modes
LCD Power Sequencing
REG03h Mode Register
LCD Enable/Disable
Introduction To Hardware Rotation
Default Portrait Mode
Hardware Rotation
Portrait
Alternate Portrait Mode
REG0Eh Screen 1 Start Word Address MSB
REG1Bh Portrait Mode Register
REG0Ch Screen 1 Start Word Address LSB
REG0Dh Screen 1 Start Word Address MSB
Epson Research and Development
Limitations
Default and Alternate Portrait Mode Comparison
Default Portrait Mode Alternate Portrait Mode
Power of 2. In most cases, a virtual
Examples
Vancouver Design Center
16 , 000 FrameRate
Vancouver Design Center
Identifying the S1D13705
Introduction
Contents of the Halstruct
Hardware Abstraction Layer HAL
Function Description
Using the HAL library
API for 13705HAL
Register / Memory Access
SeSetInit
Initialization
Int seRegisterDeviceconst Lphalstruc lpHalInfo
Int seGetIdint * pId
General HAL Support
Int seGetBytesPerScanlineint * pBytes
Int seSetBitsPerPixelint BitsPerPixel
Int seGetBitsPerPixelint * pBitsPerPixel
Int seGetLastUsableBytelong * plLastByte
Int seDelayint MilliSeconds
Int seGetScreenSizeint * Width, int * Height
Int seSetHWRotateint Rotate
Advanced HAL Functions
Int seSetHighPerformanceBOOL OnOff
Int seSetPortraitMethod int Style
Int seSplitScreenint Screen, int VisibleScanlines
Int seSplitInitWORD Scrn1Addr, Word Scrn2Addr
SeVirtInit must be been called before calling seVirtMove
Int seVirtInitDWORD VirtX, Dword * VirtY
Int seVirtMoveint Screen, int x, int y
Int seReadDisplayByteDWORD Offset, Byte *pByte
Register / Memory Access
Int seGetRegint Index, Byte * pValue
Int seSetRegint Index, Byte Value
Int seWriteDisplayBytesDWORD Offset, Byte Value, Dword Count
Int seReadDisplayDwordDWORD Offset, Dword *pDword
Int seSetPowerSaveModeint PwrSaveMode
Int seDrawLineint x1, int y1, int x2, int y2, Dword Color
Drawing
Int seSetPixellong x, long y, Dword Color
Int seGetPixellong x, long y, Dword *pColor
Int seGetLutBYTE *pLUT, int Count
LUT Manipulation
Int seSetLutBYTE *pLut, int Count
Int seGetLutEntryint index, Byte *pEntry
Int seSetLutEntryint Index, Byte *pEntry
Porting Libse to a new target platform
Building the HAL library for the target example
Building the Libse library for SH3 target example
Sample Code
Sample code using the S1D13705 HAL API
Epson Research and Development
Purple
Sample code without using the S1D13705 HAL API
Pbyte
Vancouver Design Center
Pclk
Vancouver Design Center
Epson Research and Development
Vancouver Design Center
NULL, OPENEXISTING,FILEATTRIBUTENORMAL, Null
Vancouver Design Center
Bool
Header Files
Sizeversion
Errfailed
Function PROTO-TYPES
HAL EXE
Vancouver Design Center
Epson Research and Development
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X27A-R-001-03
S1D13705 Register Summary X27A-R-001-03 01/02/13
Document Number X27A-B-001-03
13705CFG Configuration Program
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13705CFG
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S1D13705 Supported Evaluation Platforms
13705CFG
Usage
Installation
General Tab
13705CFG Configuration Tabs
If your hardware implementation differs from
Decode Addresses
Values for the Register address and Display
Ation platform are examples of possible implementa
Display which requires more memory but uses less
Power
Preferences Tab
For details see the S1D13705 Hardware Functional
Specification, document number X27A-A-001-xx
Clocks Tab
Down list or by entering the desired frequency in MHz
Actual Clki frequency used for configuration is
Source for both Pclk and Mclk
Clki frequency must be selected from the drop
Panel Tab
These settings define the polarity of the Fpline
Ically for configuring 8-bit color STN panels
8 bit. When an active panel type is selected
When the panel type is TFT, Single is automatically
Refer to S1D13705 Hardware Functional Specifi
Cation, document number X27A-A-001-xx, for a
Complete description of the Fpframe pulse settings
Panel manufacturers recommended settings. If the file
Settings contained in the file
Hardware Power Save function is not available
Panel Power Tab
GPIO0 is enabled. When this box is unchecked,
Registers Tab
Open
13705CFG Menus
Save As
Save
Configure Multiple
Export
About 13705CFG
Enable Tooltips
Comments
ERD on the Web
Document No. X27A-B-002-02
13705SHOW Demonstration Program
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13705SHOW
PC platform at the prompt, type
Download the program 13705SHOW to the system
Use alternate portrait mode
Continuously update display memory
Program Messages
Error Did not find a 13705 device
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Document No. X27A-B-003-02
13705SPLT Display Utility
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13705SPLT
Manual mode Move Screen 2 up Move Screen 2 down
Enables manual split screen operation
Enables automatic split screen operation
Timer is used to move screen
13705SPLT Example
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Document No. X27A-B-004-02
13705VIRT Display Utility
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13705VIRT
Enable alternate portrait mode. Selecting this
Defaults to virtual width = = physical width x
Force landscape display mode to be set
Force portrait display mode to be set
Virtual screen shows in the lower left
13705VIRT Example
Virtual screen shows in the upper right
Display
Unable to use virtual mode at xx BPP
Document No. X27A-B-005-04
13705PLAY Diagnostic Utility
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13705PLAY
Writes data to the register specified by the index
Writes data to the LUT index when data is
Download the program 13705PLAY to the system
Reads/writes the registers
13705PLAY Example
Scripting
Program Messages
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Document No. X27A-B-006-03
13705BMP Demonstration Program
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13705BMP currently views only Windows BMP format images
13705BMP
At the prompt, type
Error Did not find an S1D13705 device
This error message should never bee seen. Contact ERD
Document No. X27A-B-007-03
13705PWR Power Save Utility
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13705PWR
Displays this usage message
Sets enables hardware power save mode REG03h bit
Download the program 13705PWR to the system
Error Did not find a 13705 device
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Document Number X27A-E-001-03
Windows CE 2.x Display Drivers
X27A-E-001-03
Windows CE 2.x Display Drivers
Example Driver Builds
With this line Ddi.dll $FLATRELEASEDIR\EPSON.dll
Ddi.dll $FLATRELEASEDIR\ddivga2.dll NK SH
Ddi.dll $FLATRELEASEDIR\ddivga8.dll NK SH
Ddi.dll $FLATRELEASEDIR\ddis364.dll
Vancouver Design Center
If CEPCDDIS1D13705
Find the section shown below, and insert the lines as marked
Endif
Ddi.dll $FLATRELEASEDIR\ddis364.dll NK SH
Epson Research and Development
Copy NK.BIN and HIMEM.SYS to c\ Boot the system
Installation for Cepc Environment
Compile Switches
Configuration
Mode File
Comments
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Document Number X27A-E-002-03
Wind River WindML v2.0 Display Drivers
X27A-E-002-03 Issue Date 01/04/06
Wind River WindML v2.0 Display Drivers
Building a WindML v2.0 Display Driver
If necessary, generate a new mode0.h configuration file
Make CPU=PENTIUM ugl
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Document Number X27A-E-003-02
Wind River UGL v1.2 Display Drivers
X27A-E-003-02 Issue Date 01/02/13
Wind River UGL v1.2 Display Drivers
Building a UGL v1.2 Display Driver
Epson Research and Development
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Document Number X27A-E-004-02
Linux Console Driver
X27A-E-004-02 Issue Date 01/09/19
Linux Console Driver
Building the Console Driver for Linux Kernel
Epson Research and Development
Vancouver Design Center
To the directory /usr/src/linux/drivers/video/epson
Vancouver Design Center
Epson Research and Development
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Document Number X27A-E-005-01
QNX Photon v2.0 Display Driver
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QNX Photon v2.0 Display Driver
Build the Driver
Configure the Driver
Building the Photon v2.0 Display Driver
Unpack the Graphics Driver Development Kit Archive
Run the Driver
Installing the Driver
Comments
Document No. X00A-E-003-04
S1D13XXX 32-Bit Windows Device Driver Installation Guide
X00A-E-003-04 Issue Date 01/04/17
Video Controller S1D13xxx Display Type
S1D13XXX 32-Bit Windows Device Driver Installation Guide
Driver Requirements
Windows NT Version
All ISA Bus Evaluation Cards
Windows
All PCI Bus Evaluation Cards
Windows 98/ME
ADD/NEW Hardware
Windows 95 OSR2
Previous Versions of Windows
All ISA Bus Evaluation Cards
Document Number X27A-G-005-03
S5U13705B00C Rev .0 ISA Bus
S1D13705 X27A-G-005-03 Issue Date 01/02/13
Parts List Schematic Diagrams
Installation and Configuration
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S1D13705B00C Schematic Diagram 1 of 4
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Features
Host Bus Selection
Installation and Configuration
Configuration DIP Switch Settings
Iovdd Selection
Jumper Settings
RD/WR# Signal Selection Pulled up to Iovdd No Connection
BS# Signal Selection Pulled up to Iovdd No Connection
Even
LCD Signal Connector J5 Pinout
Pins
LCD Interface Pin Mapping
Comments
CPU/Bus Interface Connector Pinouts
CPU/BUS Connector H1 Pinout
Connector
CPU/BUS Connector H2 Pinout
DB150 D150 WE1#
Host Bus Interface Pin Mapping
Embedded Memory Support
Technical Description
Expanded Memory Manager Support
ISA Bus Support
Non-ISA Bus Support
Display Adapter Card Support
Clock Input Support
Decoding Logic
Color Passive LCD Panel Support
LCD Panel Voltage Setting
Power Save Modes
Monochrome LCD Panel Support
13 CPU/Bus Interface Header Strips
Adjustable LCD Panel Negative Power Supply
Adjustable LCD Panel Positive Power Supply
Item # Qty/board Designation Part Value Description
Parts List
S1D13705B00C Schematic Diagram 1
Schematic Diagrams
S1D13705B00C
Vancouver Epson Research
S1D13705B00C Schematic Diagram 4
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Document Number X27A-G-014-02
S1D13705 X27A-G-014-02 Issue Date 2002/09/16
LCD Interface Pin Mapping Technical Description
Introduction Features Installation and Configuration
Parts List Schematics Board Layout Technical Support
CPU Interface
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Configuration DIP Switch SW1 Location
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Introduction
Features
Configuration DIP Switch SW1 Location
Configuration DIP Switches
Not Used SW1-6
SH-4
SH-3
Big Endian bus interface Little Endian bus interface SW1-5
PCI Bridge Fpga
Configuration Jumpers
Jumper Summary
Jumper Function Position No Jumper
Configuration Jumper JP2 Location
Configuration Jumper JP4 Location
Configuration Jumper JP6 Location
CPU Interface Pin Mapping
CPU Interface
CPU Interface Pin Mapping
Connector Comments Pin No
CPU Bus Connector Pin Mapping
CPU Bus Connector H1 Pinout
CPU Bus Connector H2 Pinout
Dual
LCD Signal Connector J5
2LCDPWR on J5 can be inverted by setting JP6 to
S1D13705 Embedded Memory
Adjustable LCD Panel Positive Power Supply Vddh
PCI Bus Support
Direct Host Bus Interface Support
Passive/Active LCD Panel Support
Adjustable LCD Panel Negative Power Supply Vlcd
Clock Options
Software
Document Sources
References
Documents
Quantity Reference Part Description
Pin DIP socket Machined socket, 8-pin
RD-0412 Xentek RD-0412, positive power Supply
EPN001 Xentek EPN001, negative power Supply
EPF6016TC144-2 Altera EPF6016TC144-2
S1D13705B00C Schematics 1
Schematics
S1D13705B00C
Schematics 2
S1D13705B00C Schematics 3
S1D13705B00C Schematics 4
S1D13705B00C Schematics 5
Board Layout
Epson LCD Controllers S1D13705
Technical Support
Document Number X27A-E-006-01
Windows CE 3.x Display Drivers
X27A-E-006-01
Windows CE 3.x Display Drivers
Example Driver Builds
If CEPCDDIS1D13X0X
Ddi.dll $FLATRELEASEDIR\ddiflat.dll NK SH
If Cepcddiflat If CEPCDDIS1D13X0X
Endif
Epson Research and Development
Installation for Cepc Environment
EnablePreferVmem
GrayPalette
Resource Management Issues
Vancouver Design Center
Simple Display Driver Configuration
Comments
Document Number X27A-G-004-02
Interfacing to the Toshiba Mips TMPR3912 Microprocessor
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Software Technical Support
Using the ITE IT8368E PC Card Buffer
Direct Connection to the Toshiba TMPR3912
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S1D13705 to TMPR3912 Direct Connection
S1D13705 to TMPR3912 Connection Using an IT8368E
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Introduction
Interfacing to the TMPR3912
AB151 A151
S1D13705 Host Bus Interface
Host Bus Pin Connection
S1D13705 Generic #1 Generic #2 Pin Names
Generic #1 Interface Mode
Generic #2 Interface Mode
General Description
Direct Connection to the Toshiba TMPR3912
Big Endian
S1D13705 Configuration
S1D13705 Configuration for Direct Connection
Memory Mapping and Aliasing
Hardware Description
Using the ITE IT8368E PC Card Buffer
S1D13705 to TMPR3912 Connection Using an IT8368E
At 128K byte intervals
IT8368E Configuration
16M byte Card 1 IO
16M byte
32M byte Card 2 Attribute
S1D13705 Configuration Using the IT8368E
= configuration for connection using ITE IT8368E
16M byte Card 2 IO
Software
Integrated Technology Express, Inc
Toshiba Mips TMPR3912 Processor ITE IT8368E
Japan North America Taiwan, R.O.C
Europe Hong Kong Singapore
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Document Number X27A-G-006-02
S1D13705 Power Consumption
S1D13705 Power Consumption X27A-G-006-02
S1D13705 Power Consumption
Conditions
S1D13705 Total Power Consumption
Summary
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Document Number X27A-G-007-04
X27A-G-007-04 Issue Date 01/02/13
Interfacing to the MC68VZ328
Introduction Interfacing to the MC68328
Interfacing to the MC68EZ328
Technical Support
List of Tables
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Introduction
Chip-Select Module
Interfacing to the MC68328
MC68328 System Bus
WE0# Connect to IO V DD
S1D13705 Host Bus Interface
Host Bus Pin Connection
S1D13705 MC68K #1 Generic #1 Pin Names
Generic #1 Interface Mode
3 MC68K #1 Interface Mode
Hardware Description
Using The MC68K #1 Host Bus Interface
MC68328 To S1D13705 Interface
Using The Generic #1 Host Bus Interface
Host Bus Interface Selection
2 S1D13705 Hardware Configuration
3 MC68328 Chip Select Configuration
Summary of Power-On/Reset Options
Epson Research and Development
MC68EZ328 System Bus
Interfacing to the MC68EZ328
S1D13705 Generic #1 Pin Names
Generic #1 Interface Mode
MC683EZ28 To S1D13705 Interface
= configuration for MC68EZ328 support
3 MC68EZ328 Chip Select Configuration
Epson Research and Development
MC68VZ328 System Bus
Interfacing to the MC68VZ328
S1D13705 Host Bus Interface
Generic #1 Interface Mode
3 MC68K #1 Interface Mode
MC68VZ328 To S1D13705 Interface
CSB1 CS#
= configuration for MC68VZ328 support
3 MC68VZ328 Chip Select and Pin Configuration
Software
Motorola Inc. Motorola Literature Distribution Center, 800
Motorola Dragonball Processors
Document Number X27A-G-008-02
Interfacing to the NEC VR4102/VR4111 Microprocessor
X27A-G-008-02 Issue Date 01/02/13
Epson LCD Controllers S1D13705 NEC Electronics Inc
Host Bus Pin Connection Generic #2 Interface Mode
Introduction Interfacing to the NEC VR4102/VR4111
VR4102/VR4111 to S1D13705 Interface
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NEC VR4102/VR4111 Read/Write Cycles
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Introduction
Overview
Interfacing to the NEC VR4102/VR4111
NEC VR4102/VR4111 System Bus
Lcdrdy
LCD Memory Access Cycles
S1D13705 Generic #2 Pin Names
Generic #2 Interface Mode
Busclk BS# RD/WR#
VR4102/VR4111 to S1D13705 Interface
See Host Bus Selection table below
S1D13705 Hardware Configuration
NEC VR4102/VR4111 Configuration
Software
References
Santa Clara California Tel 800 Fax 800
NEC Electronics Inc
NEC Electronics Inc. U.S.A
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Document Number X27A-G-009-02
Interfacing to the PC Card Bus
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PC Card to S1D13705 Interface
Memory Access Cycles
Interfacing to the PC Card Bus
S1D13705 Bus Interface
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PC Card Read Cycle
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Introduction
PC Card Overview
Memory Access Cycles
Interfacing to the PC Card Bus
PC Card System Bus
PC Card Read Cycle
S1D13705 Bus Interface
Generic #2 Interface Mode
Hardware Connections
PC Card to S1D13705 Interface
Register/Memory Mapping
Signal Low High
Software
PC Card Pcmcia Standard March
Pcmcia
PC Card Standard
Document Number X27A-G-010-02
Interfacing to the Motorola MPC821 Microprocessor
X27A-G-010-02 Issue Date 01/02/13
MPC821 to S1D13705 Interface
Host Bus Interface Modes Generic #1 Host Bus Interface Mode
Introduction Interfacing to the MPC821
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List of Tables
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Introduction
MPC821 Bus Overview
Interfacing to the MPC821
MPC8xx System Bus
Normal Non-Burst Bus Transactions
Power PC Memory Read Cycle
Burst Cycles
Power PC Memory Write Cycle
General-Purpose Chip Select Module Gpcm
Memory Controller Module
User-Programmable Machine UPM
Host Bus Interface Modes
Generic #1 Host Bus Interface Mode
Typical Implementation of MPC821 to S1D13705 Interface
MPC821 to S1D13705 Interface
List of Connections from MPC821ADS to S1D13705
MPC821ADS Evaluation Board Hardware Connections
P12-A5, P12-B5, P12-A6, P12-B6
P6-A14 WE0#
P12-A1, P12-B1, P12-A2, P12-B2
P12-A3, P12-B3, P12-A4, P12-B4
Configuration Settings
MPC821 Chip Select Configuration
1FFE0
Test Software
Epson Research and Development
Software
Motorola Inc. Literature Distribution Center 800
Motorola MPC821 Processor
Epson LCD/CRT Controllers S1D13705
Document Number X27A-G-011-02
Interfacing to the Motorola MCF5307 ColdFire Microprocessor
X27A-G-011-02 Issue Date 01/02/13
Epson LCD Controllers S1D13705 Motorola MCF5307 Processor
Host Bus Pin Connection Generic #1 Interface Mode
Introduction Interfacing to the MCF5307
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List of Tables
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Introduction
MCF5307 System Bus
Interfacing to the MCF5307
MCF5307 Memory Read Cycle
Chip-Select Module
S1D13705 Bus Interface
Generic #1 Interface Mode
Typical Implementation of MCF5307 to S1D13705 Interface
MCF5307 To S1D13705 Interface
Little Endian Big Endian = configuration for MFC5307 support
MCF5307 Chip Select Configuration
Software
References
Motorola MCF5307 Processor
Document Number X27A-G-012-02
Interfacing to the Philips Mips PR31500/PR31700 Processor
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Direct Connection to the Philips PR31500/PR31700
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S1D13705 to PR31500/PR31700 Direct Connection
S1D13705 to PR31500/PR31700 Connection Using an IT8368E
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Introduction
Interfacing to the PR31500/PR31700
S1D13705 Host Bus Interface
Generic #1 Interface Mode
Generic #2 Interface Mode
S1D13705 to PR31500/PR31700 Direct Connection
Direct Connection to the Philips PR31500/PR31700
Memory Mapping and Aliasing
S1D13705 Configuration and Pin Mapping
Using the ITE IT8368E PC Card Buffer
S1D13705 to PR31500/PR31700 Connection Using an IT8368E
S1D13705 S1D13705 aliased 128 times 0900 0000h
S1D13705 Configuration
Software
Philips Semiconductors
Philips Mips PR31500/PR31700 Processor
Document Number X00A-G-004-02
S5U13704/5 TMPR3912/22U CPU Module
S5U13704/5 TMPR3912/22U CPU Module
Table of Contents
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List of Figures
List of Tables
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General Description
Bus Interface Modes
S1D13704/5 Bus Interface
Generic #2 Interface Mode
Hardware Connections
TMPR3912/22U and S1D13704/5 Interface
S1D13704/5 Generic #2 Interface Pin Mapping
S1D13704/5 Configuration and Pin Mapping
= configuration for Toshiba TMPR3912/22U host bus interface
Memory Mapping and Aliasing
Clki
Clock Signals Busclk
LCD Connectors 1 50-pin LCD Module Connector, J3
CPU Module Description
3 S1D13704\75 Chip Select
Standard Epson LCD Connector, J4
LCD Controller 1 S1D13704 vs. S1D13705
Lcdpwr Polarity
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Document Number X27A-G-013-02
Interfacing to the NEC VR4181A Microprocessor
X27A-G-013-02
VR4181A to S1D13705 Interface
NEC VR4181A System Bus Overview LCD Memory Access Signals
Introduction Interfacing to the NEC VR4181A
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Typical Implementation of VR4181A to S1D13705 Interface
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Introduction
NEC VR4181A System Bus
Interfacing to the NEC VR4181A
LCD Memory Access Signals
BHE#
Generic #2 Interface Mode
Typical Implementation of VR4181A to S1D13705 Interface
VR4181A to S1D13705 Interface
S1D13705 Hardware Configuration
NEC VR4181A Configuration
Software
References
Technical Support
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Document Number X27A-G-015-01
Interfacing to an 8-bit Processor
X27A-G-015-01 Issue Date 01/12/20
Epson LCD/CRT Controllers S1D13705
Interfacing to an 8-bit Processor
Generic 8-bit Processor System Bus
Bit Processor to S1D13705 Interface
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List of Tables
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Introduction
Generic 8-bit Processor System Bus
Interfacing to an 8-bit Processor
S1D13705 Generic #2 Description Pin Names
Generic #2 Interface Mode
Bit Processor to S1D13705 Interface
Little Endian Big Endian
= required configuration for this application
Software
References
Technical Support
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