Page 8 Epson Research and Development
Vancouver Design Center
S1D13705 Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
X27A-G-011-02 Issue Date: 01/02/13
2 Interfacing to the MCF5307

2.1 The MCF5307 System Bus

The MCF5200/5300 family of processors feature a high-speed synchronous system bus
typical of modern microprocessors. This section is an overview of the operation of the CPU
bus to establish interface requirements.
2.1.1 Overview
The MCF5307 microprocessor family uses a synchronous address and data bus, very
similar in architecture to the MC68040 and MPC8xx. All outputs and inputs are timed with
respect to a square-wave reference clock calle d BCLK0 (Master Clock). This clock runs at
a software-selectable divisor rate from the machine cycle speed of t he CPU cor e, typi call y
20 to 33 MHz. Both the address and the data bus are 32 bits in width. All IO accesses are
memory-mapped; there is no separate IO spac e in the Coldfire architecture.
The bus can support two types of cycles, normal and burst. Burst memory cycles are used
to fill on-chip cache memories, and for certain on-chip DMA oper ations. Normal cycles are
used for all other data transfers.

2.1.2 Normal (Non-Burst) Bus Transactions

A data transfer is initiated by the bus master by placing the memory address on address
lines A31 through A0 and driving TS (Transfer Start) low for one clock cycle. Several
control signals are also provided with the memory address:
• SIZ[1:0] (Transfer Size), which indicate whe ther the bus cycle is 8, 16, or 32 bits in
width.
•R/W
, which is high for read cycles and low for wr ite cycles.
• A set of transfer type signals (TT[1:0]) which pro vide more detail on the type of transfer
being attempted.
•TIP
(Transfer In Progress), which is asserted wh e never a bus cycle is active.
When the peripheral device being accessed ha s completed the bus transfer, it asserts TA
(Transfer Acknowledge) for one clock cycle, completing the bus tra nsaction. Once TA has
been asserted, the MCF5307 will not start another bus cycle until TA has been de-asserted.
The minimum length of a bus transaction is two bus clocks.
Figure 2-1 illustrates a typical memory read cycle on the MCF5307 system bus, and Figure
2-2 illustrates a memory write cycle.