Epson Research and Development Page 27
Vancouver Design Center
Hardware Functional Specification S1D13705
Issue Date: 02/02/01 X27A-A-001-10
Note
CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 84
Table 7-1: SH-4 Timing
Symbol Parameter Min Max Units
fCKIO Bus Clock frequency 50 MHz
TCKIO Bus Clock period 1/fCKIO
t2 Bus Clock pulse width low 8ns
t3 Bus Clock pulse width high 8ns
t4 A[16:0], RD/WR# setup to CKIO 0ns
t5 A[16:0], RD/WR# hold from CS# 0ns
t6 BS# setup 5ns
t7 BS# hold 5ns
t8 CSn# setup 0ns
t9 Falling edge RD# to DB[15:0] driven 25 ns
t10 CKIO to WE#, RD# high 1.5TCKIO
t11 Rising edge CSn# to RDY# high impedance TCKIO
t12 Falling edge CSn# to RDY# driven 20 ns
t13 CKIO to RDY# low 20 ns
t14 Rising edge CSn# to RDY# high 16 ns
t15 DB[15:0] setup to 2nd CKIO after BS# (write cycle) 0ns
t16 DB[15:0] hold (write cycle) 0ns
t17 RDY# falling edge to DB[15:0] valid (read cycle) 7ns
t18 Rising edge RD# to DB[15:0] high impedance (read cycle) 10 ns