Epson S1D13705 Symbol Parameter Min Max Units, Bus Clock frequency MHz, Bus Clock period

Epson Research and Development	Page 27
Vancouver Design Center

Table 7-1: SH-4 Timing

Symbol	Parameter	Min	Max	Units
fCKIO	Bus Clock frequency		50	MHz
TCKIO	Bus Clock period	1/fCKIO
t2	Bus Clock pulse width low	8		ns
t3	Bus Clock pulse width high	8		ns
t4	A[16:0], RD/WR# setup to CKIO	0		ns
t5	A[16:0], RD/WR# hold from CS#	0		ns
t6	BS# setup	5		ns
t7	BS# hold	5		ns
t8	CSn# setup	0		ns
t9	Falling edge RD# to DB[15:0] driven		25	ns
t10	CKIO to WE#, RD# high	1.5TCKIO
t11	Rising edge CSn# to RDY# high impedance		TCKIO
t12	Falling edge CSn# to RDY# driven		20	ns
t13	CKIO to RDY# low		20	ns
t14	Rising edge CSn# to RDY# high		16	ns
t15	DB[15:0] setup to 2nd CKIO after BS# (write cycle)	0		ns
t16	DB[15:0] hold (write cycle)	0		ns
t17	RDY# falling edge to DB[15:0] valid (read cycle)		7	ns
t18	Rising edge RD# to DB[15:0] high impedance (read cycle)		10	ns

Note

CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 84

Hardware Functional Specification	S1D13705
Issue Date: 02/02/01	X27A-A-001-10