Epson S1D13705 technical manual X27A-R-001-03

S1D13705 Register Summary

REG[00h]

R

C

R

1

IO address = 1FFE0h

2

, RO

EVISION

ODE

EGISTER

Product Code = 001001

Revision Code = 00

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 1

Bit 0

REG[01h]

M

ODE

R

EGISTER

0

IO address = 1FFE1h, RW

Color/Mono3

FPLine

FPFrame

Mask

Data Width

4

TFT/STN

Dual/Single

Polarity

Polarity

FPSHIFT

Bit 1

Bit 0

REG[02h]

M

ODE

R

EGISTER

1

IO address = 1FFE2h, RW

Bit-Per-Pixel

3

High 5

Input Clock

Display

Frame

Hw Video

Software

Bit 1

Bit 0

Performance

Div (CLKI/2)

Blank

Repeat

Invert

Video Invert

Enable

REG[03h]

M

ODE

R

EGISTER

2

IO address = 1FFE3h, RW

LCDPWR

Hardware

Sw Power Save

6

n/a

n/a

n/a

n/a

Override

PS Enable

Bit 1

Bit 0

REG[04h]

H

ORIZONTAL

P

ANEL

S

IZE

R

EGISTER

IO address = 1FFE4h, RW

n/a

Horizontal Panel Size = 8(REG + 1)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[05h]

V

ERTICAL

P

ANEL

S

IZE

R

EGISTER

(LSB)

IO address = 1FFE5h, RW

Vertical Panel Size = (REG[05h], REG[06h]) + 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[06h]

V

ERTICAL

P

ANEL

S

IZE

R

EGISTER

(MSB)

IO address = 1FFE6h, RW

n/a

n/a

n/a

n/a

n/a

n/a

Vertical Panel Size

Bit 9

Bit 8

REG[07h]

FPL

INE

S

TART

P

OSITION

IO address = 1FFE7h, RW

n/a

n/a

n/a

FPLine Start Position = 8(REG[07h] + 2)

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[08h]

H

ORIZONTAL

N

ON

-D

ISPLAY

P

ERIOD

IO address = 1FFE8h, RW

n/a

n/a

n/a

Horizontal Non-Display Period = 8(REG + 4)

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[09h]

FPF

RAME

S

TART

P

OSITION

IO address = 1FFE9h, RW

n/a

n/a

FPFrame Start Position

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[0Ah]

V

ERTICAL

N

ON

-D

ISPLAY

P

ERIOD

R

EGISTER

IO address = 1FFEAh, RW

Vert Non-

n/a

Vertical Non-Display Period

Disp Status

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[0Bh]

MOD R

ATE

R

EGISTER

IO address = 1FFEBh, RW

n/a

n/a

MOD Rate

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[0Ch]

S

CREEN

1 S

TART

W

ORD

A

DDRESS

R

EGISTER

(LSB)

IO address = 1FFECh, RW

Screen 1 Start Word Address = (REG[0Ch], REG[0Dh], REG[10] bit 1)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[0Dh]

S

CREEN

1 S

TART

W

ORD

A

DDRESS

R

EGISTER

(MSB)

IO address = 1FFEDh, RW

Screen 1 Start Word Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

REG[0Eh] S

CREEN

2 S

TART

W

ORD

A

DDRESS

R

EGISTER

(LSB)

IO address = 1FFEEh, RW

Screen 2 Start Word Address = (REG[0E], REG[0Fh], REG[10] bit 4)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

REG[0Fh] S

CREEN

2 S

TART

W

ORD

A

DDRESS

R

EGISTER

(MSB)

IO address = 1FFEFh, RW

Screen 2 Start Word Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

REG[10h]

S

CREEN

S

TART

A

DDRESS

O

VERFLOW

R

EGISTER

)

IO address = 1FFF0h, RW

Screen 2

Screen 1

Start Add

Start Add

Bit 16

Bit 16

REG[11h] MEMORY ADDRESS OFFSET REGISTER IO address = 1FFF1h, RW

			Memory Address Offset
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
REG[12h] SCREEN 1 VERTICAL SIZE REGISTER (LSB)				IO address = 1FFF2h, RW
		Screen 1 Vertical Size = (REG[12h], REG[13h])
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
REG[13h] SCREEN 1 VERTICAL SIZE REGISTER (MSB) IO address = 1FFF3h, RW
n/a	n/a	n/a	n/a	n/a	n/a	Screen 1 Vertical Size
						Bit 9	Bit 8
REG[15h] LOOK-UP TABLE ADDRESS REGISTER IO address = 1FFF5h, RW
			Look-Up Table Address
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
REG[17h] LOOK-UPTABLE DATA REGISTER IO address = 1FFF7h, RW
	Look-Up Table Data			n/a	n/a	n/a	n/a
Bit 3	Bit 2	Bit 1	Bit 0
REG[18h] GPIO CONFIGURATION CONTROL REGISTER				IO address = 1FFF8h, RW
n/a	n/a	n/a	GPIO4 Pin	GPIO3 Pin	GPIO2 Pin	GPIO1 Pin	GPIO0 Pin
			IO Config	IO Config	IO Config	IO Config	IO Config
REG[19h] GPIO STATUS / CONTROL REGISTER IO address = 1FFF9h, RW
n/a	n/a	n/a	GPIO4 Pin	GPIO3 Pin	GPIO2 Pin	GPIO1 Pin	GPIO0 Pin
			IO Status	IO Status	IO Status	IO Status	IO Status
REG[1Ah] SCRATCH PAD REGISTER IO address = 1FFFAh, RW
			Scratch Pad Register
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
REG[1Bh] SWIVELVIEW MODE REGISTER IO address = 1FFFBh, RW
SwivelView	SwivelView	n/a	n/a	n/a	reserved	SwivelView PCLK Select
Mode En.	Mode Sel.					Bit 1	Bit 0
REG[1Ch] LINE BYTE COUNT REGISTER IO address = 1FFFCh, RW
			Line Byte Count
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0

Notes

1These bits are used to identify the S1D13705 at power on / reset.

2IO addresses are relative to the beginning of display memory.

3Gray Shade/Color Mode Selection

Color/Mono	Bit-Per-Pixel Bit 1	Bit-Per-Pixel Bit 0	Display Mode
REG[01] bit 5	REG[02] bit 7	REG[02] bit 6
	0	0	2 Colors	1 Bit-Per-Pixel
1		1	4 Colors	2 Bit-Per-Pixel
	1	0	16 Colors	4 Bit-Per-Pixel
		1	256 Colors	8 Bit-Per-Pixel
	0	0	2 Gray Shade	1 Bit-Per-Pixel
0		1	4 Gray Shade	2 Bit-Per-Pixel
	1	0	16 Gray Shade	4 Bit-Per-Pixel
		1	reserved

X27A-R-001-03

4	Panel Data Format
	TFT/STN		Color/	Dual/	Data			Data
					Width			Width
			Mono	Single
	REG[01]				Bit 1			Bit 0			Function
			REG[01]	REG[01]
	bit 7				REG[01]			REG[01]
			bit 5	bit 6
					bit 1			bit 0
					0			0		Mono Single 4-bit LCD
				0				1		Mono Single 8-bit LCD
					1			0			reserved
			0					1			reserved
					0			0			reserved
				1				1		Mono Dual 8-bit LCD
					1			0			reserved
	0							1			reserved
					0			0		Color Single 4-bit LCD
				0				1		Color Single 8-bit LCD Format 1
					1			0			reserved
			1					1		Color Single 8-bit LCD Format 2
					0			0			reserved
				1				1		Color Dual 8-bit LCD
					1			0			reserved
								1			reserved
	1			don’t care				0		9 bit TFT Panel
								1		12 bit TFT Panel
5	High Performance Selection
				Bit-Per-Pixel		Bit-Per-Pixel
	High Performance			Bit 1			Bit 0			Display Modes
				REG[02] bit 7		REG[02] bit 6
				0			0		MClk = PClk/8		1 bit-per-pixel
		0					1		MClk = PClk/4		2 bit-per-pixel
				1			0		MClk = PClk/2		4 bit-per-pixel
							1		MClk = PClk		8 bit-per-pixel
		1		X			X			MClk = PClk
6 Power Save Mode Selection
	Power Save Bit 1			Power Save Bit 0						Mode
		0			0				Power Save Mode 1
		0			1					reserved
		1			0					reserved
		1			1				Normal Operation

Page 1 01/02/13