QNX Photon v2.0 Display Driver | Epson S1D13705 specification

Epson Research and Development	Page 3
Vancouver Design Center

QNX Photon v2.0 Display Driver

The Photon v2.0 display drivers for the S1D13705 Color LCD Controller are intended as “reference” source code for OEMs developing for QNX platforms. The driver package provides support for 8 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13705. Source code modification is required to provide a smaller driver for mass production.

The current revision of the driver is designed for use with either QNX RTP or QNX4 from the latest product CD (Dec. 99).

The Photon v2.0 display driver is designed around a common configuration include file called S1D13705.h, which is generated by the configuration utility 13705CFG. This design allows for easy customization of display type, clocks, decode addresses, etc. by OEMs. For further information on 13705CFG, see the 13705CFG Configuration Program User Manual, document number X27A-B-001-xx.

Note

The QNX display drivers are provided as “reference” source code only. They are intend- ed to provide a basis for OEMs to develop their own drivers for QNX Photon v2.0.

This document and the source code for the QNX display drivers are updated as appropriate. Please check the Epson Electronics America website at http://www.eea.epson.com or the Epson Research and Development website at http://www.erd.epson.com for the latest revisions before beginning any development.

We appreciate your comments on our documentation. Please contact us via e-mail at documentation@erd.epson.com.

QNX Photon v2.0 Display Driver	S1D13705
Issue Date: 01/09/10	X27A-E-005-01

Image 277

Epson S1D13705 technical manual QNX Photon v2.0 Display Driver

Contents

Document No. X27A-Q-001-04 S1D13705 This page Left Blank Customer Support Information This page Left Blank February S1D13705 Embedded Memory LCD Controller Embedded 80K byte Sram display buffer Software Suspend mode LCD power-down sequencing Document Number X27A-A-001-10 Hardware Functional Specification This page Left Blank Table of Contents Registers Power Save ModesSwivelView Mechanical Data List of Tables This page Left Blank List of Figures 2 Bit-per-pixel Monochrome Mode Data Output Path Scope IntroductionOverview Description Integrated Frame Buffer FeaturesCPU Interface Display Support Clock Source Display ModesMiscellaneous Package Typical System Diagram SH-4 Bus Typical System Implementation Diagrams Typical System Diagram M68K #1 Bus Typical System Diagram Generic #1 Bus Functional Block Descriptions Functional Block DiagramHost Interface Memory Controller Power Save contains the power save mode circuitry Power SaveLook-Up Table LCD Interface Pinout Diagram PinsPackage type 80 pin surface mount QFP14 Key Pin DescriptionPin Names Type Pin # Cell Description Input This pin inputs the chip select signal For SH-3/SH-4 mode, this pin inputs the write enable signalFor MC68K #1, this pin inputs the R/W# signal For the lower data byte WE0# Pin Name Type Pin # Cell Clock Input Power SupplyMiscellaneous Pin Name Type Pin # Driver Description Summary of Power On/Reset Options Summary of Configuration OptionsHost Bus Interface Pin Mapping Host Bus Interface Pin Mapping LCD Interface Pin Mapping LCD Interface Pin MappingBit Pin Name Bit Dual Single 12-bit Format Input Specifications C. CharacteristicsAbsolute Maximum Ratings Recommended Operating Conditions for Core VDD = 3.3V ± 10% Output Specifications 1 SH-4 Interface Timing Bus Interface Timing Bus Clock frequency MHz Symbol Parameter Min Max UnitsBus Clock period T11 Rising edge CSn# to RDY# high impedance T12 T13 2 SH-3 Interface TimingT14 T15 D150 Write T16 T17 D150 Symbol Parameter Min Maxa Units AS# high to DTACK# high AS# high to DTACK# high impedance Motorola MC68K #1 Interface TimingUDS#, LDS# falling edge to D150 valid write cycle AS# high to DSACK1# high AS# high to DSACK1# high impedance Motorola MC68K #2 Interface TimingDS# falling edge to D3116 valid write cycle AS#, DS# rising edge to D3116 high impedance Generic #1 Timing Generic #1 Interface Timing Generic #2 Timing Generic #2 Interface Timing Input Clock Frequency Clki MHz Clock Input RequirementsInput Clock period Clki Input Clock Pulse Width High Clki Input Clock period Bclk Input Clock Frequency Bclk MHzInput Clock Pulse Width High Bclk Symbol Parameter Min Typ Max Units Power On/Reset TimingDisplay Interface REG03h to FPLINE, FPFRAME, FPSHIFT, FPDAT, Drdy Lcdpwr Override REG03h bit HW Power Save Power Down/Up TimingREG03h bits FP Signals Active Inactive Active Inactive 11 Single Monochrome 4-Bit Panel Timing Single Monochrome 4-Bit Panel Timing Data Timing Sync Timing 13 Single Monochrome 8-Bit Panel Timing Single Monochrome 8-Bit Panel Timing = REG08h bits 4-0 x 8 + 4Ts 15 Single Color 4-Bit Panel Timing Single Color 4-Bit Panel Timing = REG08h bits 4-0 x 8 + 1.5Ts 17 Single Color 8-Bit Panel Timing Format Single Color 8-Bit Panel Timing Format T6a T6b T7a T14 T11 19 Single Color 8-Bit Panel Timing Format = REG08h bits 4-0 x 8 + 1Ts 21 Dual Monochrome 8-Bit Panel Timing Dual Monochrome 8-Bit Panel Timing = REG04h bits 6-0+1 x 8 + REG08h bits 4-0 + 4 x 8 x 2Ts 23 Dual Color 8-Bit Panel Timing Dual Color 8-Bit Panel Timing = REG08h bits 4-0 x 2x 8 + 17Ts 25 12-Bit TFT/D-TFD Panel Timing 10 9/12-Bit TFT/D-TFD Panel Timing 26 TFT/D-TFD A.C. Timing 18 TFT/D-TFD A.C. Timing Register Mapping RegistersRegister Descriptions Bit Panel Data Format Active highColor/Mono Dual/Single Data Width Bit Function Don’t care Color/Mono Bit-Per-Pixel Bit Display Mode Gray Scale/Color Mode SelectionHigh Performance Selection High Performance BPP Bit Display Modes Inverse Video Mode Select Options Video Mode Select Options belowVideo data is inverted after the Look-Up Table Software Power Save Mode Selection Hardware Power Save/GPIO0 Operation Vertical Panel This register must not be set to a value less than 03hSize Bit Fpline Start Following constraint must be satisfied MOD Rate Bit Vertical Non Screen 2 Start Screen 1 Start Offset Bit MemoryVertical Size Bit LUT Address Screen-Register Relationship, Split Screen LUT Data Bit REG18h Gpio Configuration Control Register SwivelView Mode Enable Mode Select Selection of SwivelView Mode Create a virtual image in SwivelView mode Selection of Pclk and Mclk in SwivelView ModePixel Clock Pclk Select Mode Enable Mode Select Where CLK is Clki REG02h bit 4 = 0 or CLKI/2 REG02h bit 4 = Frame Rate Calculation Passive Dual-Panel modeTFT/D-TFD and Passive Single-Panel modes 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization Display Data Formats Look-Up Table Architecture Bit-per-pixel Monochrome modeMonochrome Modes Green Look-Up Table LUT is used for all monochrome modes 4 Bit-per-pixel Monochrome Mode Data Output Path Color Modes Bit-per-pixel Color Mode 2 Bit-per-pixel Color Mode Data Output Path 4 Bit-per-pixel Color Mode Data Output Path 8 Bit-per-pixel Color Mode Data Output Path SwivelView Default SwivelView Mode Where bpp is bits-per-pixel and bpb is bits-per-byte How to Set Up Default SwivelView ModeWhere bpb is bits-per-byte and bpp is bits-per-pixel Start Address 480 Image refreshed by S1D13705 Alternate SwivelView Mode How to Set Up Alternate SwivelView Mode SwivelView Mode Limitations Comparison Between Default and Alternate SwivelView ModesDefault and Alternate SwivelView Mode Comparison Default SwivelView Mode Alternate SwivelView Mode Software Power Save Mode Power Save ModesHardware Power Save Mode Panel Power Up/Down Sequence Power Save Mode Function SummaryPower Save Mode Function Summary Hardware Software Normal Software Power Save Turning Off Bclk Between Accesses S1D13705 Internal Clock Requirements Clock Requirements QFP14 80 pin Unit mm Mechanical Data14.0 ± 12.0 ± Index 125 Japan North America Taiwan Sales and Technical Support This page Left Blank Document Number X27A-G-002-03 Programming Notes and Examples This page Left Blank Introduction Initialization LCD Power Sequencing and Power Save ModesMemory Models Look-Up Table LUT Sample Code Identifying the S1D13705 Hardware Abstraction Layer HAL S1D13705 Initialization Sequence This page Left Blank Introduction Display Buffer Location InitializationRegister Values S1D13705 Initialization Sequence Frame Rate CalculationRegister Value hex See Also For a dual passive panel the formula is Where Pclk = Pixel clock in Hz= Horizontal Display Period in pixels = Horizontal Non-Display Period in pixels Epson Research and Development 1 Bit-Per-Pixel 2 Colors/Gray Shades Memory ModelsBit Pixel 4 Bit-Per-Pixel 16 Colors/Gray Shades 2 Bit-Per-Pixel 4 Colors/Gray ShadesPixel Bit Green bit Eight Bit-Per-Pixel 256 Colors Look-Up Table LUT LUT Data Look-Up Table Registers Color Modes Look-Up Table OrganizationIndex Red Green Blue Unused entries Indicates unused entries Example LUT Values for 2 Bpp Color Mode Bpp color Index Index Recommended LUT Values for 1 Bpp Gray Shade Gray Shade ModesAddress Red Green Blue Suggested Values for 2 Bpp Gray Shade Suggested LUT Values for 4 Bpp Gray Shade Virtual Display Advanced Techniques Examples RegistersREG11h Memory Address Offset Register Offset Panning and Scrolling REG0Ch Screen 1 Display Start Address 0 LSB Number of Pixels Panned Using Start AddressREG0Dh Screen 1 Display Start Address 1 MSB REG10h Screen 1 Display Start Address 2 MSB Panning to the left To scroll down 320x240 Single Panel For Split Screen Split Screen REG13 Screen 1 Vertical Size MSB REG12 Screen 1 Vertical Size LSB REG0Fh Screen 2 Display Start Address 1 MSB REG0Eh Screen 2 Display Start Address 0 LSB Examples LCD Power Sequencing LCD Power Sequencing and Power Save ModesREG03h Mode Register Hardware Software Power Save Override Enable Bit LCD Enable/Disable Hardware Rotation Default Portrait ModeIntroduction To Hardware Rotation Portrait Alternate Portrait Mode REG0Ch Screen 1 Start Word Address LSB REG1Bh Portrait Mode RegisterREG0Dh Screen 1 Start Word Address MSB REG0Eh Screen 1 Start Word Address MSB Epson Research and Development Default Portrait Mode Alternate Portrait Mode Default and Alternate Portrait Mode ComparisonPower of 2. In most cases, a virtual Limitations Examples Vancouver Design Center 16 , 000 FrameRate Vancouver Design Center Identifying the S1D13705 Hardware Abstraction Layer HAL Contents of the HalstructIntroduction API for 13705HAL Using the HAL libraryFunction Description Register / Memory Access Int seRegisterDeviceconst Lphalstruc lpHalInfo InitializationSeSetInit Int seGetIdint * pId General HAL Support Int seGetBitsPerPixelint * pBitsPerPixel Int seSetBitsPerPixelint BitsPerPixelInt seGetBytesPerScanlineint * pBytes Int seGetScreenSizeint * Width, int * Height Int seDelayint MilliSecondsInt seGetLastUsableBytelong * plLastByte Int seSetHighPerformanceBOOL OnOff Advanced HAL FunctionsInt seSetPortraitMethod int Style Int seSetHWRotateint Rotate Int seSplitScreenint Screen, int VisibleScanlines Int seSplitInitWORD Scrn1Addr, Word Scrn2Addr Int seVirtMoveint Screen, int x, int y Int seVirtInitDWORD VirtX, Dword * VirtYSeVirtInit must be been called before calling seVirtMove Int seGetRegint Index, Byte * pValue Register / Memory AccessInt seSetRegint Index, Byte Value Int seReadDisplayByteDWORD Offset, Byte *pByte Int seWriteDisplayBytesDWORD Offset, Byte Value, Dword Count Int seReadDisplayDwordDWORD Offset, Dword *pDword Int seSetPowerSaveModeint PwrSaveMode Int seSetPixellong x, long y, Dword Color DrawingInt seGetPixellong x, long y, Dword *pColor Int seDrawLineint x1, int y1, int x2, int y2, Dword Color Int seSetLutBYTE *pLut, int Count LUT ManipulationInt seGetLutBYTE *pLUT, int Count Int seGetLutEntryint index, Byte *pEntry Int seSetLutEntryint Index, Byte *pEntry Porting Libse to a new target platform Building the HAL library for the target example Building the Libse library for SH3 target example Sample Code Sample code using the S1D13705 HAL API Epson Research and Development Purple Sample code without using the S1D13705 HAL API Pbyte Vancouver Design Center Pclk Vancouver Design Center Epson Research and Development Vancouver Design Center NULL, OPENEXISTING,FILEATTRIBUTENORMAL, Null Vancouver Design Center Bool Header Files Sizeversion Errfailed Function PROTO-TYPES HAL EXE Vancouver Design Center Epson Research and Development This page Left Blank X27A-R-001-03 S1D13705 Register Summary X27A-R-001-03 01/02/13 Document Number X27A-B-001-03 13705CFG Configuration Program This page Left Blank 13705CFG This page Left Blank S1D13705 Supported Evaluation Platforms 13705CFG Usage Installation General Tab 13705CFG Configuration Tabs Values for the Register address and Display Decode AddressesAtion platform are examples of possible implementa If your hardware implementation differs from Preferences Tab PowerDisplay which requires more memory but uses less Clocks Tab Specification, document number X27A-A-001-xxFor details see the S1D13705 Hardware Functional Source for both Pclk and Mclk Actual Clki frequency used for configuration isClki frequency must be selected from the drop Down list or by entering the desired frequency in MHz Panel Tab 8 bit. When an active panel type is selected Ically for configuring 8-bit color STN panelsWhen the panel type is TFT, Single is automatically These settings define the polarity of the Fpline Refer to S1D13705 Hardware Functional Specifi Panel manufacturers recommended settings. If the file Complete description of the Fpframe pulse settingsSettings contained in the file Cation, document number X27A-A-001-xx, for a GPIO0 is enabled. When this box is unchecked, Panel Power TabHardware Power Save function is not available Registers Tab Open 13705CFG Menus Save As Save Configure Multiple Export Comments Enable TooltipsERD on the Web About 13705CFG Document No. X27A-B-002-02 13705SHOW Demonstration Program This page Left Blank 13705SHOW Use alternate portrait mode Download the program 13705SHOW to the systemContinuously update display memory PC platform at the prompt, type Program Messages Error Did not find a 13705 device This page Left Blank Document No. X27A-B-003-02 13705SPLT Display Utility This page Left Blank 13705SPLT Enables automatic split screen operation Enables manual split screen operationTimer is used to move screen Manual mode Move Screen 2 up Move Screen 2 down 13705SPLT Example This page Left Blank Document No. X27A-B-004-02 13705VIRT Display Utility This page Left Blank 13705VIRT Force landscape display mode to be set Defaults to virtual width = = physical width xForce portrait display mode to be set Enable alternate portrait mode. Selecting this Virtual screen shows in the upper right 13705VIRT ExampleDisplay Virtual screen shows in the lower left Unable to use virtual mode at xx BPP Document No. X27A-B-005-04 13705PLAY Diagnostic Utility This page Left Blank 13705PLAY Download the program 13705PLAY to the system Writes data to the LUT index when data isReads/writes the registers Writes data to the register specified by the index 13705PLAY Example Scripting Program Messages This page Left Blank Document No. X27A-B-006-03 13705BMP Demonstration Program This page Left Blank At the prompt, type 13705BMP13705BMP currently views only Windows BMP format images Error Did not find an S1D13705 device This error message should never bee seen. Contact ERD Document No. X27A-B-007-03 13705PWR Power Save Utility This page Left Blank 13705PWR Download the program 13705PWR to the system Sets enables hardware power save mode REG03h bitDisplays this usage message Error Did not find a 13705 device This page Left Blank Document Number X27A-E-001-03 Windows CE 2.x Display Drivers X27A-E-001-03 Windows CE 2.x Display Drivers Example Driver Builds Ddi.dll $FLATRELEASEDIR\ddivga8.dll NK SH Ddi.dll $FLATRELEASEDIR\ddivga2.dll NK SHDdi.dll $FLATRELEASEDIR\ddis364.dll With this line Ddi.dll $FLATRELEASEDIR\EPSON.dll Vancouver Design Center If CEPCDDIS1D13705 Find the section shown below, and insert the lines as marked Endif Ddi.dll $FLATRELEASEDIR\ddis364.dll NK SH Epson Research and Development Copy NK.BIN and HIMEM.SYS to c\ Boot the system Installation for Cepc Environment Compile Switches Configuration Mode File Comments This page Left Blank Document Number X27A-E-002-03 Wind River WindML v2.0 Display Drivers X27A-E-002-03 Issue Date 01/04/06 Wind River WindML v2.0 Display Drivers Building a WindML v2.0 Display Driver If necessary, generate a new mode0.h configuration file Make CPU=PENTIUM ugl This page Left Blank Document Number X27A-E-003-02 Wind River UGL v1.2 Display Drivers X27A-E-003-02 Issue Date 01/02/13 Wind River UGL v1.2 Display Drivers Building a UGL v1.2 Display Driver Epson Research and Development This page Left Blank Document Number X27A-E-004-02 Linux Console Driver X27A-E-004-02 Issue Date 01/09/19 Linux Console Driver Building the Console Driver for Linux Kernel Epson Research and Development Vancouver Design Center To the directory /usr/src/linux/drivers/video/epson Vancouver Design Center Epson Research and Development This page Left Blank Document Number X27A-E-005-01 QNX Photon v2.0 Display Driver This page Left Blank QNX Photon v2.0 Display Driver Building the Photon v2.0 Display Driver Configure the DriverUnpack the Graphics Driver Development Kit Archive Build the Driver Run the Driver Installing the Driver Comments Document No. X00A-E-003-04 S1D13XXX 32-Bit Windows Device Driver Installation Guide X00A-E-003-04 Issue Date 01/04/17 Driver Requirements S1D13XXX 32-Bit Windows Device Driver Installation GuideWindows NT Version Video Controller S1D13xxx Display Type All PCI Bus Evaluation Cards WindowsAll ISA Bus Evaluation Cards Windows 98/ME ADD/NEW Hardware Windows 95 OSR2 Previous Versions of Windows All ISA Bus Evaluation Cards Document Number X27A-G-005-03 S5U13705B00C Rev .0 ISA Bus S1D13705 X27A-G-005-03 Issue Date 01/02/13 Parts List Schematic Diagrams Installation and Configuration This page Left Blank S1D13705B00C Schematic Diagram 1 of 4 This page Left Blank Features Configuration DIP Switch Settings Installation and ConfigurationHost Bus Selection RD/WR# Signal Selection Pulled up to Iovdd No Connection Jumper SettingsBS# Signal Selection Pulled up to Iovdd No Connection Iovdd Selection Pins LCD Signal Connector J5 PinoutLCD Interface Pin Mapping Even CPU/BUS Connector H1 Pinout CPU/Bus Interface Connector PinoutsConnector Comments CPU/BUS Connector H2 Pinout DB150 D150 WE1# Host Bus Interface Pin Mapping Embedded Memory Support Technical Description Non-ISA Bus Support ISA Bus SupportDisplay Adapter Card Support Expanded Memory Manager Support Clock Input Support Decoding Logic Power Save Modes LCD Panel Voltage SettingMonochrome LCD Panel Support Color Passive LCD Panel Support Adjustable LCD Panel Positive Power Supply Adjustable LCD Panel Negative Power Supply13 CPU/Bus Interface Header Strips Item # Qty/board Designation Part Value Description Parts List S1D13705B00C Schematic Diagram 1 Schematic Diagrams S1D13705B00C Vancouver Epson Research S1D13705B00C Schematic Diagram 4 This page Left Blank Document Number X27A-G-014-02 S1D13705 X27A-G-014-02 Issue Date 2002/09/16 Parts List Schematics Board Layout Technical Support Introduction Features Installation and ConfigurationCPU Interface LCD Interface Pin Mapping Technical Description This page Left Blank Configuration DIP Switch SW1 Location This page Left Blank Introduction Features Configuration DIP Switch SW1 Location Configuration DIP Switches SH-3 SH-4Big Endian bus interface Little Endian bus interface SW1-5 Not Used SW1-6 Jumper Summary Configuration JumpersJumper Function Position No Jumper PCI Bridge Fpga Configuration Jumper JP2 Location Configuration Jumper JP4 Location Configuration Jumper JP6 Location CPU Interface Pin Mapping CPU InterfaceCPU Interface Pin Mapping CPU Bus Connector H1 Pinout CPU Bus Connector Pin MappingConnector Comments Pin No CPU Bus Connector H2 Pinout 2LCDPWR on J5 can be inverted by setting JP6 to LCD Signal Connector J5Dual PCI Bus Support Adjustable LCD Panel Positive Power Supply VddhDirect Host Bus Interface Support S1D13705 Embedded Memory Passive/Active LCD Panel Support Adjustable LCD Panel Negative Power Supply Vlcd Clock Options Software Documents ReferencesDocument Sources Quantity Reference Part Description EPN001 Xentek EPN001, negative power Supply RD-0412 Xentek RD-0412, positive power SupplyEPF6016TC144-2 Altera EPF6016TC144-2 Pin DIP socket Machined socket, 8-pin S1D13705B00C Schematics 1 Schematics S1D13705B00C Schematics 2 S1D13705B00C Schematics 3 S1D13705B00C Schematics 4 S1D13705B00C Schematics 5 Board Layout Epson LCD Controllers S1D13705 Technical Support Document Number X27A-E-006-01 Windows CE 3.x Display Drivers X27A-E-006-01 Windows CE 3.x Display Drivers Example Driver Builds If CEPCDDIS1D13X0X Ddi.dll $FLATRELEASEDIR\ddiflat.dll NK SH If Cepcddiflat If CEPCDDIS1D13X0X Endif Epson Research and Development Installation for Cepc Environment EnablePreferVmem GrayPalette Resource Management Issues Vancouver Design Center Simple Display Driver Configuration Comments Document Number X27A-G-004-02 Interfacing to the Toshiba Mips TMPR3912 Microprocessor This page Left Blank Direct Connection to the Toshiba TMPR3912 Using the ITE IT8368E PC Card BufferSoftware Technical Support This page Left Blank S1D13705 to TMPR3912 Direct Connection S1D13705 to TMPR3912 Connection Using an IT8368E This page Left Blank Introduction Interfacing to the TMPR3912 Host Bus Pin Connection S1D13705 Host Bus InterfaceS1D13705 Generic #1 Generic #2 Pin Names AB151 A151 Generic #1 Interface Mode Generic #2 Interface Mode General Description Direct Connection to the Toshiba TMPR3912 S1D13705 Configuration for Direct Connection S1D13705 ConfigurationMemory Mapping and Aliasing Big Endian Hardware Description Using the ITE IT8368E PC Card Buffer S1D13705 to TMPR3912 Connection Using an IT8368E 16M byte Card 1 IO IT8368E Configuration16M byte At 128K byte intervals = configuration for connection using ITE IT8368E S1D13705 Configuration Using the IT8368E16M byte Card 2 IO 32M byte Card 2 Attribute Software Japan North America Taiwan, R.O.C Toshiba Mips TMPR3912 Processor ITE IT8368EEurope Hong Kong Singapore Integrated Technology Express, Inc This page Left Blank Document Number X27A-G-006-02 S1D13705 Power Consumption S1D13705 Power Consumption X27A-G-006-02 S1D13705 Power Consumption Conditions S1D13705 Total Power Consumption Summary This page Left Blank Document Number X27A-G-007-04 X27A-G-007-04 Issue Date 01/02/13 Interfacing to the MC68EZ328 Introduction Interfacing to the MC68328Interfacing to the MC68VZ328 Technical Support List of Tables This page Left Blank Introduction MC68328 System Bus Interfacing to the MC68328Chip-Select Module Host Bus Pin Connection S1D13705 Host Bus InterfaceS1D13705 MC68K #1 Generic #1 Pin Names WE0# Connect to IO V DD Generic #1 Interface Mode 3 MC68K #1 Interface Mode MC68328 To S1D13705 Interface Using The MC68K #1 Host Bus InterfaceHardware Description Using The Generic #1 Host Bus Interface 3 MC68328 Chip Select Configuration 2 S1D13705 Hardware ConfigurationSummary of Power-On/Reset Options Host Bus Interface Selection Epson Research and Development MC68EZ328 System Bus Interfacing to the MC68EZ328 S1D13705 Generic #1 Pin Names Generic #1 Interface Mode MC683EZ28 To S1D13705 Interface = configuration for MC68EZ328 support 3 MC68EZ328 Chip Select Configuration Epson Research and Development MC68VZ328 System Bus Interfacing to the MC68VZ328 S1D13705 Host Bus Interface Generic #1 Interface Mode 3 MC68K #1 Interface Mode MC68VZ328 To S1D13705 Interface CSB1 CS# = configuration for MC68VZ328 support 3 MC68VZ328 Chip Select and Pin Configuration Software Motorola Inc. Motorola Literature Distribution Center, 800 Motorola Dragonball Processors Document Number X27A-G-008-02 Interfacing to the NEC VR4102/VR4111 Microprocessor X27A-G-008-02 Issue Date 01/02/13 Introduction Interfacing to the NEC VR4102/VR4111 Host Bus Pin Connection Generic #2 Interface ModeVR4102/VR4111 to S1D13705 Interface Epson LCD Controllers S1D13705 NEC Electronics Inc This page Left Blank NEC VR4102/VR4111 Read/Write Cycles This page Left Blank Introduction NEC VR4102/VR4111 System Bus Interfacing to the NEC VR4102/VR4111Overview Lcdrdy LCD Memory Access Cycles S1D13705 Generic #2 Pin Names Generic #2 Interface Mode Busclk BS# RD/WR# VR4102/VR4111 to S1D13705 Interface See Host Bus Selection table below S1D13705 Hardware Configuration NEC VR4102/VR4111 Configuration Software References NEC Electronics Inc. U.S.A NEC Electronics IncSanta Clara California Tel 800 Fax 800 This page Left Blank Document Number X27A-G-009-02 Interfacing to the PC Card Bus This page Left Blank Interfacing to the PC Card Bus Memory Access CyclesS1D13705 Bus Interface PC Card to S1D13705 Interface This page Left Blank PC Card Read Cycle This page Left Blank Introduction Interfacing to the PC Card Bus Memory Access CyclesPC Card System Bus PC Card Overview PC Card Read Cycle S1D13705 Bus Interface Generic #2 Interface Mode Hardware Connections PC Card to S1D13705 Interface Register/Memory Mapping Signal Low High Software PC Card Pcmcia Standard March Pcmcia PC Card Standard Document Number X27A-G-010-02 Interfacing to the Motorola MPC821 Microprocessor X27A-G-010-02 Issue Date 01/02/13 Introduction Interfacing to the MPC821 Host Bus Interface Modes Generic #1 Host Bus Interface ModeMPC821 to S1D13705 Interface This page Left Blank List of Tables This page Left Blank Introduction MPC8xx System Bus Interfacing to the MPC821MPC821 Bus Overview Normal Non-Burst Bus Transactions Power PC Memory Read Cycle Burst Cycles Power PC Memory Write Cycle General-Purpose Chip Select Module Gpcm Memory Controller Module User-Programmable Machine UPM Host Bus Interface Modes Generic #1 Host Bus Interface Mode Typical Implementation of MPC821 to S1D13705 Interface MPC821 to S1D13705 Interface List of Connections from MPC821ADS to S1D13705 MPC821ADS Evaluation Board Hardware Connections P12-A1, P12-B1, P12-A2, P12-B2 P6-A14 WE0#P12-A3, P12-B3, P12-A4, P12-B4 P12-A5, P12-B5, P12-A6, P12-B6 Configuration Settings MPC821 Chip Select Configuration 1FFE0 Test Software Epson Research and Development Software Motorola Inc. Literature Distribution Center 800 Motorola MPC821 Processor Epson LCD/CRT Controllers S1D13705 Document Number X27A-G-011-02 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X27A-G-011-02 Issue Date 01/02/13 Introduction Interfacing to the MCF5307 Host Bus Pin Connection Generic #1 Interface ModeEpson LCD Controllers S1D13705 Motorola MCF5307 Processor This page Left Blank List of Tables This page Left Blank Introduction MCF5307 System Bus Interfacing to the MCF5307 MCF5307 Memory Read Cycle Chip-Select Module S1D13705 Bus Interface Generic #1 Interface Mode Typical Implementation of MCF5307 to S1D13705 Interface MCF5307 To S1D13705 Interface Little Endian Big Endian = configuration for MFC5307 support MCF5307 Chip Select Configuration Software References Motorola MCF5307 Processor Document Number X27A-G-012-02 Interfacing to the Philips Mips PR31500/PR31700 Processor This page Left Blank Direct Connection to the Philips PR31500/PR31700 This page Left Blank S1D13705 to PR31500/PR31700 Direct Connection S1D13705 to PR31500/PR31700 Connection Using an IT8368E This page Left Blank Introduction Interfacing to the PR31500/PR31700 S1D13705 Host Bus Interface Generic #1 Interface Mode Generic #2 Interface Mode S1D13705 to PR31500/PR31700 Direct Connection Direct Connection to the Philips PR31500/PR31700 Memory Mapping and Aliasing S1D13705 Configuration and Pin Mapping Using the ITE IT8368E PC Card Buffer S1D13705 to PR31500/PR31700 Connection Using an IT8368E S1D13705 S1D13705 aliased 128 times 0900 0000h S1D13705 Configuration Software Philips Semiconductors Philips Mips PR31500/PR31700 Processor Document Number X00A-G-004-02 S5U13704/5 TMPR3912/22U CPU Module S5U13704/5 TMPR3912/22U CPU Module Table of Contents This page Left Blank List of Figures List of Tables This page Left Blank General Description Bus Interface Modes S1D13704/5 Bus Interface Generic #2 Interface Mode Hardware Connections TMPR3912/22U and S1D13704/5 Interface = configuration for Toshiba TMPR3912/22U host bus interface S1D13704/5 Configuration and Pin MappingMemory Mapping and Aliasing S1D13704/5 Generic #2 Interface Pin Mapping LCD Connectors 1 50-pin LCD Module Connector, J3 Clock Signals BusclkCPU Module Description Clki LCD Controller 1 S1D13704 vs. S1D13705 Standard Epson LCD Connector, J4Lcdpwr Polarity 3 S1D13704\75 Chip Select This page Left Blank Document Number X27A-G-013-02 Interfacing to the NEC VR4181A Microprocessor X27A-G-013-02 Introduction Interfacing to the NEC VR4181A NEC VR4181A System Bus Overview LCD Memory Access SignalsVR4181A to S1D13705 Interface This page Left Blank Typical Implementation of VR4181A to S1D13705 Interface This page Left Blank Introduction NEC VR4181A System Bus Interfacing to the NEC VR4181A LCD Memory Access Signals BHE# Generic #2 Interface Mode Typical Implementation of VR4181A to S1D13705 Interface VR4181A to S1D13705 Interface S1D13705 Hardware Configuration NEC VR4181A Configuration Software References Technical Support This page Left Blank Document Number X27A-G-015-01 Interfacing to an 8-bit Processor X27A-G-015-01 Issue Date 01/12/20 Generic 8-bit Processor System Bus Interfacing to an 8-bit ProcessorBit Processor to S1D13705 Interface Epson LCD/CRT Controllers S1D13705 This page Left Blank List of Tables This page Left Blank Introduction Generic 8-bit Processor System Bus Interfacing to an 8-bit Processor S1D13705 Generic #2 Description Pin Names Generic #2 Interface Mode Bit Processor to S1D13705 Interface Little Endian Big Endian = required configuration for this application Software References Technical Support This page Left Blank