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Epson Research and Development

 

Vancouver Design Center

 

 

REG[0Ah] Vertical Non-Display Period

 

 

 

 

 

Address = 1FFEAh

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

Vertical Non-

 

 

Vertical Non-

Vertical Non-

Vertical Non-

Vertical Non-

Vertical Non-

Vertical Non-

Display

 

n/a

Display

Display

Display

Display

Display

Display

Status

 

 

Period Bit 5

Period Bit 4

Period Bit 3

Period Bit 2

Period Bit 1

Period Bit 0

 

 

 

 

 

 

 

 

 

bit 7

Vertical Non-Display Status

 

This bit =1 during the Vertical Non-Display period.

bits 5-0

Vertical Non-Display Period

 

These bits specify the vertical non-display period. This register is programmed as follows:

 

VerticalNonDisplayPeriod(lines ) = REG[0Ah] bits [5:0]

Note

This register should be set only once, on power-up during initialization.

.

REG[0Bh] MOD Rate Register

 

 

 

 

 

Address = 1FFEBh

 

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

n/a

 

n/a

 

MOD Rate

MOD Rate

MOD Rate

MOD Rate

MOD Rate

MOD Rate

 

 

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

bits 5-0

 

MOD Rate Bits [5:0]

 

 

 

 

 

 

 

When the value of this register is 0, the MOD output signal toggles every FPFRAME. For

 

 

 

a non-zero value, the value in this register + 1 specifies the number of FPLINEs between

 

 

 

toggles of the MOD output signal. These bits are for passive LCD panels only.

S1D13705

Hardware Functional Specification

X27A-A-001-10

Issue Date: 02/02/01

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Image 68
Epson S1D13705 technical manual Vertical Non, MOD Rate Bit