Epson S1D13705 technical manual Bus Interface Timing, 1 SH-4 Interface Timing

Page 26 Epson Research and Development

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7 A.C. Characteristics

Conditions: IO VDD = 2.7 V to 5.0 V

TA = -40°C to 85° C

Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%)

CL = 60pF (Bus/MPU Interface)

CL = 60pF (LCD Panel Interface)

7.1 Bus Interface Timing

7.1.1 SH-4 Interface Timing

	TCKIO	t2	t3
CKIO
		t4					t5
A[16:0], M/R#
RD/WR#
		t6	t7
BS#
		t8
CSn#
			t9		t10		t11
WEn#
RD#
			t12	t13			t14
RDY#
				t15		t16
D[15:0]
	Hi-Z						Hi-Z
(write)
					t17		t18
D[15:0]	Hi-Z					VALID	Hi-Z
(read)
				Figure 7-1: SH-4 Timing

Note

The SH-4 Wait State Control Register for the area in which the S1D13705 resides must be set to

anon-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK).

S1D13705	Hardware Functional Specification
X27A-A-001-10	Issue Date: 02/02/01