Epson Research and Development

Page 5

Vancouver Design Center

 

 

 

 

 

List of Tables

 

Table 3-1:

Configuration DIP Switch Settings

10

Table 3-2:

Jumper Summary

11

Table 4-1:

CPU Interface Pin Mapping

15

Table 4-2:

CPU Bus Connector (H1) Pinout

16

Table 4-3:

CPU Bus Connector (H2) Pinout

17

Table 5-1:

LCD Signal Connector (J5)

18

List of Figures

Figure 3-1: Configuration DIP Switch (SW1) Location . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3-2: Configuration Jumper (JP1) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3-3: Configuration Jumper (JP2) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3-4: Configuration Jumper (JP3) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3-5: Configuration Jumper (JP4) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-6: Configuration Jumper (JP5) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3-7: Configuration Jumper (JP6) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3-8: Configuration Jumper (JP7) Location . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10-1: S1D13705B00C Schematics (1 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10-2: S1D13705B00C Schematics (2 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 10-3: S1D13705B00C Schematics (3 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10-4: S1D13705B00C Schematics (4 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10-5: S1D13705B00C Schematics (5 of 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

S5U13705B00C Rev. 2.0 Evaluation Board User Manual

S1D13705

Issue Date: 2002/09/16

X27A-G-014-02

Page 317
Image 317
Epson S1D13705 technical manual Configuration DIP Switch SW1 Location